76
All and more about Sharp PC
-1
500 at http:
/l
www.PC-1500.info
Q)
Wa
it time
of
1/0 port controller
it
self
When the CPU accesses the If O
port
co
ntro
ll
er. wait
of
a single CPU machine cycle is
automatically
app
lied.
If the
WO
and W I is in the
wa
it state wh
en
the C
PU
accessed the 1/ 0
pon
control
l
er
.
wait e
nd
s in
on
e cy
cl
e.
NOTE: When there is
no
wait
cond
ition in
WO
and
W1. the same waveform as M
EO
and ME1
are sent
on
DMEO and
DM
E1.
I '
t<--
t
~
•os
AO
-!
1
M
EO
/I
OM
€0/
I
' '
'
'
'
'
....
.
;
....
,
tA
I>
'
'
'
~:
.
....
'
on
' '
' '
o I
' '
' '
' '
~
·
,
.._
tS
' '
'
''
' '
' '
o
o~-+-
~--
;...+
-
-C::::::::::::::::::::::::::::::::::::::::::::::::
::::::::::::
:•:•==>
I I 1 I
:-<E-
tP
~
·-
,
-----
-
IA
--
---
-,"',
o I
~---
~
~
~,__
__________
__...,
, ..
A
et
u.11
tP'
and
tA'
for
actual
ROM is
as
fo
ll
ows:
tP
' = !
AP
+ l P +
ID
I
A'
=
!A
- 10 -
IS
ts =
200nS
Since
IAP
and
t D differ dependi
ng
on
the
per
ipheral circuit configuration. they should
be
computed
on
the basis of load
ca
pacitance.
3-4-3. Seri
al
data input
SD
I
is
a serial
data
transf
er input
and
CLI
ser
ial
da
ta
transf
er
cloc
k.
The
1{ 0
pon
controller reads the
input
data
at the rising edge
of
C
LI
.
Se
rial
data
goes in
to
t
he
receiving
mode when it changes from
an
idle
state
(SD
I= I) 10 low· state
and
reads
da
ta
fr
om a next clock.
SDI
==x
__
~
X
..__
_
__,
X
'--
-
cu
When the 8-bit
data
is received.
it
sets
the
receive
and
nag
RD
active. If the mask bit is
on
at
this point, interrupt request is issued to the
CPU.
RD
will
be reset
upon
reading the 8-bit
data
.
RD
wi
ll
be
reset
in
a
co
urse
of
serial
data
receiving. which is the p
er
iod
that
the 8-bit
data
is
being received, w
it
hout including the
Stan
bit.
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not sell this PDF !! !
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