Sharp PC-1500 - Page 82

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cu
SD I
RD
3-4-4. Reset
0
234 5 67
In serial
recei
ve
t Reset as it went
int o serial data
rece
iv e.
Reset as the
CPU read th e
serial data.
When the RESET li ne is kept in ~ 1 ~ at least for thr ee 4> 0S clock cy cl es. it cau ses internal
reset. by which a ll i nt ernal r egi sters are clear ed to "O" an d ports PA and PB go into t he
input mode. TI 1e d ivi der. however. w ill not be r ese t.
Terminal stat es after the r es<:: t ar e as shown in Ta bl e below.
Pin name In/ Ou t State after reset
00 - 07 In/ Out Hi gh impe dance
PAO- PA ?
.. ..
PBO - PB7
.. ..
PCO -P C7
-1 -
Out L ow level
WAIT
..
(N OTE)
OM EO
..
"
OM E1
..
"
INT
"
Low level
soo
In/ Out Hig h level
CL O
"
Low level
NO TE: WA IT , OMEO. and OME1 are output de pendent of WO. MEO . W l , and M E1 and do no t
have any
co nnect i on with reset.
77
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