All and more about Sh
ar
p PC
-1
500 at http:/lwww.PC-1500
.in
fo
4-2. PC-1500
4-2-1 . Outline
(i)
CPU
The L
H58
01 CM
OS
8-b
it Micro
pro
cesso
r is
used
. As it
is
operated by
th
e clo
ck
frequency
of
2.6M Hz
fr
om the crystal osci
ll
at
or,
it
s internal machine cycle is I .3M Hz.
BFI .
....
. . . . . . Depression
of
the @ k
ey
turns
it
to
hi
gh
level so that
VCC
is
su
pp
lied from
BFO
.
!
NO
~
J
N?
...
. . . Input
po
n for other than
th
e
@]
key.
DO
~
D7
..
....
. . Bidirectional d
ata
bu
s which is used to w
ri
te
and
read data to/
fr
om
the external memory.
DO
: LSR
07
:
MSB
ADON
AD
15 . . . . Address bus.
A
DO
: LSB
AD
l5:
MSB
X
LO
. XL I . .
....
External crystal conn
ec
tion ter
rni
nab. through which the 2.
6MH
z
crystal is
conn
ected.
CD
1/ 0 PC
XLO
: Input
XLI
:
Ou
tput
Either L
H5
8 I 0 or LH58 I I is used The same chip is used
fo
r I/ 0
of
CE-
150.
CE
-1
53
,
and CE-
15
8.
P
AO
cv
P
A7
.
...
. K
ey
strobe output
P
B?
. . . . . . . . . . .
@]
key i
np
ut
AD0 ~
3,
AD
l
2
~
1
3
,
D~E
I
....
. . Addr
es
s
of
1/0
po
n
is
s
et.
within
FOOOH
to
FOOFH
o
ft
he MEI area.
(i)
Timer
IC
µPD
1990AC
is
used and connected with the 32.768kH7. cry
sta
l.
©
Chip
select decoder
It consists
of
two chips
of
TC4
0H
I 39F
an
d TC40H I
38F
and
it is used
to
select
ch
ip by
means of
so
~
4
,
S6
, S7, 2Y2 a
nd
2Y3.
For
mo
re de
ta
ils, refer
to
"C
hip select circuit".
<D
Display
chip
Because 4-bit SC882G
is
used, chip I is used in pair
wi
th
ch
ip 3 .and
chip
2 w
it
h chip
4.
Se
le
ct signal is
commo
nly us
ed
by chip I
and
chip 3 or chip 2 a nd c
hi
p 4.
Da
ta bus is
therefore div
id
ed into D0- 0 3
an
d
04
-
07
in order I(> handle compatible with the 8-
bit RAM.
Ad
dr
ess is
wi
thin 7600H to
77FFH
of
the MEO
ar
ea
an
d
is
used for the
fix
ed va
ri
a
bl
e
ar
ea
. in addition lo ·the display buffe
r.
© System ROM
It
is the PC-
1500
syst
em
program residing
RO
M
fo
r whi
ch
the 8-bitX
16
K SC61328F
is
used. Address is w
it
hin
COOO
H to
FFF
FH of the MEO
ar
e
a.
(j)
System RAM
Because the 4-bitX I K bytes TC
55
I 4 is used in a
pa
ir, the data b
us
is divided into two of
00
~
03
and
04
~
07
and the select signal S7 is
co
mmon
ly
shared so as 10
be
compatible with the 8-bit RAM.
Ad
dr
ess is w
it
hin 7800H to 7BFFH of the
MEO
area which is used
fo
r the s
ys
tem
me
mor
y area
an
d for the fixed
va
riable ar
ea
.
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