B
A
0
A
ll
and more about Sharp PC-1500
at
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Truth Table
Input
Er.ISLE
SELECT
Output
G
A
B
YO
Yf
Y2
YT
YO
Yi
H
*
*
H
H H
H
L L
L L
H
H H
Y2
L
H L
H L H
H
L
L H H H
L H
L H H
H H
H L
Y3
l*=
Irrelevant
- -
• Selection
of
I
YO
- I
Y3
by the decoder
IC
(TC40H l 39H)
is
done when
the
gate signal (GI) input
BFO
is
low_
YO
With
low
state
of
AD
14
and
AD
IS.
the
YO
output
becomes
low
to
select
the
system
(!
YO)
ROM area
of
the module unit.
(0000-
3FFF
address setup)
YI With high state
of
ADl4
and
low
st
ate
of
ADl5,
the
YI
output becomes low to select
(IYI)
the gate (G2A)
of
the
IC
(TC40HB8F).
(4000-
7FFF
address setup)
Y2 With low state
of
AD14 and high state
of
AD15, the Y2 output becomes low to select
(IY2)
the
expansion
ROM
area
of
the module unlt.
(8000-
BFFF address setup)
Y3 With high state
of
AD14 and AD15, the
Y3
output becomes low
to
select the system
(IY
3) program
ROM
(CS-613128F) and the
1/0
port (LH5811).
(COOO
- FFFF address
setup)
• Selection
of
SO
- S7
by
the decoder
IC
(TC40Hl 38F) is done when t
he
gate signal input
MEO
(GI)
is
high,
YI
(G2)
low,
and
G2B
is
low
{which
is
normally
low)
.
SO
With
all
of
AD
II,
AD
12, and
AD
B
in
low state,
SO
goes
to
the low state and selects the
(YO)
RAM3 (TC5517AF).
(4000-47FF
address setup)
SI
With high state
of
ADI I and low· state
of
AD12 and AD13,
SI
goes to the low state to
(Y
I) select the option user
RAM
area.
(4800-49FF
address setup)
S2 With low state
of
AD
11
and
high
state
of
AD
12 and l
ow
state
of
AD 13, S2 goes
to
the
(Y2) low state to select the option
RAM
area. (5000 - 57FF address se·tup)
S3
Wi
th
high state
of
ADii
and
ADl2
and
low state
of
ADl3, S3 goes to the low state
to
(Y3) select the option user
RAM
area.
(6000-
67FF address setup)
S6 With low state
of
AD
11
and high state
of
AD
12
and
AD
13, S6 goes to the l
ow
state
to
(Y6) receive the interrupt input from an option into the
1{
0
part
. (
1000
- 77FF address
setup)
S7 With all
of
AD 11,
AD
12, and
AD
13
in
hi
gh
state, S7 goes to the low state to select the
(Y7) system memory
RAMI
and 2 ('TC5514P). (7800 - 7FPF addres setup) RA
M!
and
RAM2 are
4·bit
RAMs
, independently used to assume low order and high order bits
to
comprise one byte with a pair
of
4 bits each.
• Selection
of
2Y2 and 2Y3 by the decoder
IC
(TC40Hl~is
done when the gate
C>f2G
becomes
active with the selection
of
the TC40H
J38F
output, S6 (Y6).
2Y2
With low state
of
ADS
and high state
of
DMEO,
t
he
2Y2 output goes to the low state so
(V2)
tha
t the
NAND
gate output V2 is turned hlgh to select the display chip I and 3.
2Y3 Wi th high state
of
AD8
and
DMEO
.• the 2Y3 output
go
es to the· low state so that the
(V3)
NANO gate out V3 is turned high to select the display chip 2 and
4.
• Display chip (SC882G) is a 4·bit
RAM,
comprised
of
one byte
of
data
wit1
1 4 low order bits and
4 high order bits of data, so that even the chip
sel
ect signals are used
in
pair
of
chip I with chip 3
and chip 2 with chip 4.
15
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