Sharp PC-E220

-4-
(
Pin No .
11 0
Signal name I Descrip ti on
46
11 0 02 I Data bu s
47
110
D1
! D at a bus
48
11 0 DO I Da t a bu s
49
1/ 0
A1S
I Address bus
so
I
1 10 I
A14
! Address bus
S1
0
!
A13
I Addre s s bus
S2 0 A12 ! Addre s s bus
S3
0
A 11 I A ddress b u s
S 4 1/0
I
A 10 i A ddress bus
55 0
i
A9 I Address bus
S6 0
i
A8 j Address bus
S 7 110
I
A? I Addre s s bus
S8 1 1 0
i
A6 I A ddress bu s
I
S9
11 0
I AS \ A d d ress bu s
60
110
!
A4
A ddress bus
61
1/ 0
I
A3
! Address bu s
62 11 0
!
A2 Addr e ss b u s
63 1/ 0
I
A1 I Addre s s bus
64
11 0
I
AO l Add r e s s bus
65 I
I
~
! Rese t input (R ese t at LO W)
I
I Liquid c rys t a l dr iver enable sig -
66
0
I
E
nal ·
67 I
M
I Ti mer cl oc k i nput
68 I
LS'
L ow batt e ry de t ection pin . L ow
when low battery.
Low battery sy m bol lighting volt-
69
0 CAU
age detection pin. ( After turning
on the symbol , h i gh i m pedance . )
70 I
I
XTAL1
Oscilla t ion circu i t input
7 1
0
I
XTAL2
Oscilla t ion circuit outpu t
72
-
I
GND
Power source 8
7 3
0
I
CLKOUT
Osci lla t ion c l oc k outpu t
I
7 4
I
-
vcc
Powe r s ource EB
75
0
VCNT
Liquid crysta l
power ON/OFF
SW signal
76 0
i
BZ
BUZZER
I
77
1/ 0 i
M1
I Z BOCP U mac hi ne cycl e
78 I
I
KON
C N KEY i nput
79
I
I
SFT I N
SHIFT KEY input
80
I
0
I
K01 I Key strobe
Pi n No . 11 0
Signa l name
Descr i p t ion
1
0 K 02
. K e y s t r obe
2
0 K0 3
I K ey s t robe
3 0
K04
I K ey s trobe
4
0
KOS
Key strobe
s
0
K 06
Key strobe
6 0
K 0 7
I K ey strobe
7 0
KO S
K ey s t robe
8 0 K0 9
! K ey s trobe
9
0
K010
Key strobe
10 I
IA1
Key i nput
1 1
I I A2
K ey i npu t
1 2 I
i
IA3
. Ke y i nput
13 I I A4
l Ke y i nput
1 4 I I AS
Ke y i nput
1S I IA6
. K ey i npu t
1 6
I
I A ?
I Key input
17 I
I A8
K ey i nput
1 8
11 0
MRE Q
Z BOCPU memory re qu e s t signal
1 9 110 I ORQ
I Z BOCPU V O reques t s i gnal
20 I
SlJSRQ
Z BOCPU bus request s ig n al
I Expansion per i pheral rese t out -
21
0 I ORE SE T
pu t ( Active hi gh ) (40 p i n e x pan-
1 sion bus output)
22
I WAIT
i ZBOCPU wait i nput
23
I I NT 1
J ZBOCPU maskable interrupt re-
q uest
24
11 0
W'R
i Z80CPU memory write si gnal
2S
11 0
RD
I ZBOCPU memory read signal
Bank select
address (When
26 11 0 BNK3
rese tti ng, domes ti c.lforeign
s elect signal)
27 110
BNK2 Bank select address
28 0
BNK1
I Bank select address
29 0 BNKO Bank select address
Expansion memory c hi p enable
30 0 CEROM2 signal ( Outputted t o 40 p i n ex-
pans i on bus)
1
B uilt- i n system ROM ch i p e n able
31 0 CEROM1
s ign al
3 2
-
GND Reference voltage
Expansion memory ch i p enable
33
0 CE R AM2 si gnal ( Outputs t o 40 p i n expan-
sion bus. )
34 0
I
CERAM1
Bui l t -i n RAM chip e nable signal
3 5
I
I
182 J 1 1 pin ACK
36
I 1 81
J 1 1 pm DIN
3 7 0
I
XOU T C asse tt e sign al output
38
I
X I N Cassette s ignal input
39
0
I
F02
1 1 pin D O UT
40 0
F01 11 p i n BUSY
41
11 0 D7 Da t a bus
4 2 1 10
i
06
1
Da t a bus
43
1/ 0
D5 I Da t abus
44 110 0 4 I Data bu s
4 5
110
D3 ! Data bus
CPU (LZ8413M} pin signal descriptions
s:-i:sraescriptions
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