Sharp PC-E500S

5. Memory map
hy
aad
eae
&HOO000
oe
Coenen
&H10000
.
|
64KB
ead
RAM
card
es
&H20000
=
4M-ROM
CE3
(2Mb)
32KB
16KB
4
Reh
eayhece
gH40000
Fb
RAM
card
RAM
card
ai
&H47FFF
|
CE1
&H4FFFF
r
7
a
CEO
&HB0000
|
RAM
|
(32KB)
a
ea
&HCO0000
!
4M-ROM
CE2
OM)
re
&HFFFFF
§. LSI description
CPU
(SC62015)
pin
signal
description
Pin
No.
|
Signal
name
Signal
description
1
x1
O
Ceramic
oscillation
output
2
AZ
|
|
Ceramic
oscillation
input
3
X38
O
|
CR
oscillation
output
4
x4
|.
|
CR
oscillation
input
5
“YDD
re)
Display
power
(convertor)
control
output
6
|
VCC
POWER
(+)
electrode
input
pin
7
|
RESET
|
Reset
input.
Reset
at
HIGH
level.
8
GND
POWER
(-)
electrode
input
pin
9
TEST
|
|
|
Test
input
10
Ci
|
|
Cassette
signal
input
pin
11
CO
oO
|
Cassette
signal
output
pin
12
ON
|
|
ON
key
input
pin.
Normally
pulled
down
to
LOW
level.
13
WR
O
|
Write
clock.
Normally
HIGH.
14
MRQ
|
—_—
_
(Reserved)
15
K1i0
|
|
oo
| | 4 KEY input pin
2 2 | 2
22
K17
|
|
|
23
DIOO
/O
!
:
|
:
Data
bus
3
|
pio7
|
vo
|
31
|
AO
|
O
|
|
Address
bus
49
A18
O
|
50
VDISP
—
(Reserved)
51
|
VA
=
4
52
oD
O
|
Clock
output
pin
for
display
chip
53
KO15
O
SIO
PRQ
(Reserved)
54
KO14
0
HIGH
with
the
ER
OPEN
command
from
SIO
A
PC-E500S