Sharp SD-AT1000H - Page 14

SD-AT1000H
– 14 –
Figure 14 BLOCK DIAGRAM (3/10)
+5V(A)
+5V(A)
+5V(A)
+5V(D)
+3.3V(D)
SI3050LUS
3
1
AK4586VQ
43
42
41
40
38
36
34
22
21
20
19
18
17
16
15
14
13
12
8
4
3
2
1
2
11
10
9
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
23
OVF
COD_DO
COD_DI
COD_CLK
COD_CSN
DSP_SCCLK
DSP_CS
DSP_SCDIN
DSP_SCDOUT
DSP_RESET
DSP_INTREQ
DIG_FUNC+B
NONPCM
COD_CSN COD_DO
D_+5V
A_GND
A_+9V
LOUT3
ROUT3
LOUT2
ROUT2
LOUT1
ROUT1
LIN
RIN
DGND
PROTECT
NONPCM COD_CLK OVF COD_DI
PROTECT
EX_CLK
MCLK
LRCK
AUDATA0
SCLK
SDATA1
AUDATA2 AUDATA1
VCC
GND 3Y 2A 1A
12
ADC/DAC/DIR
CONVERTER
PVDD PVSS SLAVE TST RX2 I2C RX1
CAD0/CSN
SCL/CCLK
SDA/CDTI
CAD1/CDTO
INT1 INT0
MCKO
TX
XTI/EXTCLK
XTO
DZF2/OVF
VREFH
AVDD
AVSS
LIN
RIN
ROUT1
ROUT2
ROUT3
LOUT3
LOUT2
LOUT1 DVSS
DVDD
TVDD
SDTO
SDTI3
SDTI2
SDTI1
LRCK
BICK
15
14
12
11
10
9
8
7
6
5
4
3
2
1
13
CNP702
TO DISPLAY SECTION
13
12
11
10
9
8
7
6
5
4
3
2
1
TO MAIN SECTION
DIGITAL IN
MUTE
IC110
VOLTAGE
REGULATOR
D103
IC102
RX101
OPTICAL
DIGITAL IN
Q102
T
D
U
N
A
D104
CNP502
VOLTAGE
REGULATOR
IC109
TC7WU04U
DUAL2-INPUT
NAND GATE