CPU 31x-2 as DP Master/DP Slave and Direct Communication
2-23
PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP
A5E00111190-01
Event Detection
Table 2-8 shows how a DP Master CPU 31x-2 recognizes operating state
transitions of a DP Slave CPU or or data transfer interrupts.
Table 2-8 Event Detection of the CPU 31x-2 as DP Slave
Event
What Happens in the DP Slave
Bus interruption
(short-circuit, plug
disconnected)
OB 86 is called and a station failure reported
(incoming event; diagnostic address of the DP slave assigned
to the DP slave)
on peripheral access: Call of OB 122
(Peripheral access error)
DP Master:
RUN → STOP
OB 82 is called and Module fault reported
(incoming event;
diagnostic address of the DP slave assigned to the DP slave)
Variable OB82_MDL_STOP=1)
DP Master:
STOP → RUN
Call of OB82 with the message Module OK.
(outgoing event;
diagnostic address of the DP slave assigned to the DP slave)
Variable OB82_MDL_STOP=0)
Evaluation in the User Program
Table 2-9 shows you how you can, for example, evaluate RUN-STOP transitions of
the DP master in the DP slave (see Table 2-8).
Table 2-9 Evaluating RUN-STOP Transitions in the DP Master/DP Slave
In the DP Master
In the DP Slave
Diagnostic Addresses Example:
Master diagnostic address =1023
Slave diagnostic address in the master
system =1022
Diagnostic Addresses Example:
Slave diagnostic address =422
Master diagnostic address = not relevant
CPU: RUN → STOP The CPU calls OB 82 with the following
information:
OB 82_MDL_ADDR:=422
OB82_EV_CLASS:=B#16#39
(incoming event)
OB82_MDL_DEFECT:=Module fault
Tip: The CPU’s diagnostic data buffer also
contains this information
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