Contents
xiv
PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP
A5E00111190-01
Tables
1-1 The Differences in Control and Display Elements Between CPUs 1-2 . . . . . .
1-2 Using a Backup Battery or Accumulator 1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-3 Memory Cards 1-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-4 CPU Interfaces 1-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-5 Characteristics of the Clock of the CPUs 1-10 . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-6 CPU Communication Options 1-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-7 Connection Resources for CPUs 312 IFM to 316-2 DP 1-14 . . . . . . . . . . . . . . .
1-8 Communication Resources for CPU 318-2 1-15 . . . . . . . . . . . . . . . . . . . . . . . . .
1-9 Diagnostic LEDs of the CPU 1-22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-10 Start Information for OB 40 for the Interrupt Inputs
of the Integrated I/Os 1-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-11 Start Information for OB 40 for the Interrupt Inputs
of the Integrated I/Os 1-44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-12 Characteristic Features of the Integrated Inputs and Outputs
of the CPU 314 IFM 1-50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 Meaning of the BUSF LED of the CPU 31x-2 as DP Master 2-6 . . . . . . . . . . .
2-2 Reading Diagnostic Data with STEP 7 2-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 Event Detection of the CPU 31x-2 as DP Master 2-11 . . . . . . . . . . . . . . . . . . . .
2-4 Evaluating RUN-STOP Transitions of the DP Slaves in the DP Master 2-12 . .
2-5 Example of an address area configuration for transfer memory 2-15 . . . . . . . .
2-6 Meaning of the BUSF LEDs in the CPU 31x-2 as DP Slave 2-19 . . . . . . . . . . .
2-7 Fetching diagnostic data with STEP 5 and STEP 7
in the master system 2-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-8 Event Detection of the CPU 31x-2 as DP Slave 2-23 . . . . . . . . . . . . . . . . . . . . .
2-9 Evaluating RUN-STOP Transitions in the DP Master/DP Slave 2-23 . . . . . . . .
2-10 Structure of Station Status 1 (Byte 0) 2-25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-11 Structure of Station Status 2 (Byte 1) 2-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-12 Structure of Station Status 3 (Byte 2) 2-26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-13 Structure of the Master PROFIBUS Address (Byte 3) 2-27 . . . . . . . . . . . . . . . .
2-14 Structure of the Manufacturer Identification (Bytes 4 and 5) 2-27 . . . . . . . . . . .
2-15 Event Detection by CPU 31x-2 Acting as Receiver in
Direct Communication 2-33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-16 Evaluation of the Station Failure of the Sender During
Direct Communication 2-34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 Operating System Processing Times of the CPUs 3-6 . . . . . . . . . . . . . . . . . . .
3-2 Process image update of the CPUs 3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 CPU-specific Factors for the User Program Processing Time 3-7 . . . . . . . . . .
3-4 Updating the S7 Timers 3-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5 Update Time and SFB Runtimes 3-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6 Extending the Cycle by Nesting Interrupts 3-10 . . . . . . . . . . . . . . . . . . . . . . . . .
3-7 Response time of the CPUs to process interrupts 3-14 . . . . . . . . . . . . . . . . . . .
3-8 Diagnostic Interrupt Response Times of the CPUs 3-15 . . . . . . . . . . . . . . . . . .
3-9 Reproducibility of the Delay and Watchdog Interrupts of the CPUs 3-17 . . . . .