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Explains the manual's content covering configuration, communication, memory, cycle times, and technical data for CPUs.
Highlights new functionalities introduced with the CPU 319-3 PN/DP.
Details operating and display elements for CPU 31xC, including status indicators and interfaces.
Explains the function and positions of the mode selector switch for setting CPU operating modes.
Compares various CPU 31xC models based on interfaces, inputs, outputs, and functions.
Explains the meaning of LED designations, colors, and states for CPU 31xC status and error indication.
Covers operating and display elements for CPU 31x series, detailing various models.
Provides general status and error displays for CPU 31x, covering LED indicators and bus error displays.
Details the available interfaces on the CPUs, including MPI, PROFIBUS DP, PROFINET, and PtP.
Covers PROFIBUS DP interface availability, operating modes, and properties for connecting distributed I/O.
Details the PROFINET interface availability, connection to Industrial Ethernet, and related properties.
Provides an overview of communication services offered by the CPUs, including PG, OP, and S7 communication.
Details S7 communication capabilities, including server/client modes and configuration types.
Describes routing functionality, enabling access to S7 stations across subnets via gateways.
Explains PROFINET as an enhancement of PROFIBUS DP and Industrial Ethernet for automation.
Details the functionality and features of open communication protocols over Industrial Ethernet.
Explains S7 connections as communication paths and their resources.
Outlines methods for allocating S7 connections, including reservation, programming, and commissioning.
Defines DPV1 as a functional extension of DP protocol for acyclical services and its availability.
Details CPU memory areas (load, system, RAM) and their retentive properties across different states.
Describes the three main memory areas of the CPU: load memory, system memory, and working memory.
Explains how data in load, system, and RAM memory is retained across power cycles and restarts.
Shows the retentive behavior of memory objects like user programs, data blocks, and flags during state transitions.
Covers the properties and usage of the SIMATIC Micro Memory Card as a module for the CPU.
Explains functions related to generating, modifying, and deleting user programs and blocks.
Describes the process of downloading the user program from the MMC to the CPU, including load and work memory.
Covers operations like downloading new blocks, delta downloads, and uploading blocks from/to the CPU.
Explains the procedure for CPU memory reset and the behavior during a warm restart.
Explains the concept of cycle time, its components, and calculation methods.
Lists factors that cause extensions to the user program's cycle time.
Details the method for calculating cycle time, including process image update and base load factors.
Provides CPU-specific factors to calculate the user program's processing time extension.
Discusses configured communication load for PG/OP, S7, and PROFINET CBA, and its impact on cycle time.
Details how testing and commissioning functions extend cycle time, showing runtimes for status variables and block status.
Introduces response time, its definition, fluctuation width, factors, and update times.
Details conditions for achieving the shortest response time and its calculation.
Explains conditions for the longest response time and its calculation.
Suggests methods like direct I/O access or process interrupts for faster response times.
Provides an overview of how to calculate cycle and response times.
Outlines the steps to determine user program runtime, process image transfer time, and OS processing time.
Summarizes the calculation methods for shortest and longest response times.
Introduces interrupt response time, its definition, and process/diagnostic interrupt response times.
Lists minimum and maximum interrupt response times for various CPUs.
Defines reproducibility for delay and watchdog interrupts and provides associated times.
Provides examples for calculating cycle time, response time, and interrupt response time.
Demonstrates a cycle time calculation based on a specific CPU and module configuration.
Demonstrates calculating process interrupt response time considering CPU, communication load, and module delays.
Calculates process interrupt response time by summing factors like CPU response, communication extension, and module interrupt time.
Detailed technical specifications for the CPU 312C, including memory, execution times, and communication functions.
Technical data for the CPU 313C, covering memory, execution times, communication, and interfaces.
Technical specifications for CPU 313C-2 PtP and CPU 313C-2 DP, detailing memory, execution times, and interfaces.
Technical data for CPU 314C-2 PtP and CPU 314C-2 DP, including memory, execution times, and I/O specifications.
Details the arrangement, usage, parameterization, and technical data of integrated digital and analog I/Os.
Technical specifications for CPU 312, covering memory, execution times, and communication functions.
Technical data for CPU 314, detailing memory, execution times, communication, and I/O.
Technical data for CPU 315-2 DP, including memory, execution times, communication, and DP master/slave capabilities.
Technical specifications for CPU 315-2 PN/DP, covering memory, execution times, communication, and interfaces.
Technical data for CPU 317-2 DP, including memory, execution times, communication, and DP master/slave capabilities.
Technical specifications for CPU 317-2 PN/DP, covering memory, execution times, communication, and interfaces.
Technical data for CPU 319-3 PN/DP, including memory, execution times, communication, and interfaces.
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