Siemens CPU 317-2 PN/DP - Reproducibility of Time-Delay and Watchdog Interrupts; Sample Calculations; Example of Cycle Time Calculation

Cycle and reaction times
5.6 Sample calculations
CPU 31xC and CPU 31x, Technical Data
5-22 Manual, 01/2006 Edition, A5E00105475-06
5.5.2 Reproducibility of Time-Delay and Watchdog Interrupts
Definition of "Reproducibility"
Delay interrupt:
The period that expires between the call of the first instruction in the interrupt OB and the
programmed time of interrupt.
Watchdog interrupt:
The fluctuation width of the interval between two successive calls, measured between the
respective initial instructions of the interrupt OBs.
Reproducibility
The following times apply for the CPUs described in this manual, with the exception of
CPU 319
• Delay interrupt: +/- 200 μs
• Watchdog interrupt: +/- 200 μs
The following times apply in the case of CPU 319:
• Delay interrupt: +/- 140 μs
• Watchdog interrupt: +/- 88 μs
These times only apply if the interrupt can actually be executed at this time and if not
interrupted, for example, by higher-priority interrupts or queued interrupts of equal priority.
5.6 5.6 Sample calculations
5.6.1 Example of cycle time calculation
Design
You have configured an S7300 and equipped it with following modules in rack "0":
• a CPU 314C-2
• 2 digital input modules SM 321; DI 32 x 24 VDC (4 bytes each in the PI)
• 2 digital output modules SM 322; DO 32 x 24 VDC/0.5 A (4 bytes each in the PI)
User Program
According to the Instruction List, the user program runtime is 5 ms. There is no active
communication.