Technical data of CPU 31x
7.6 CPU 317-2 DP
CPU 31xC and CPU 31x, Technical Data
7-28 Manual, 01/2006 Edition, A5E00105475-06
Technical Data
FCs See the Instruction List
• Number
2048
(in the 0 to 2047 range of numbers)
• Size
64 KB
Address areas (I/O)
Total I/O address area Max. 8192 bytes / 8192 bytes
(can be freely addressed)
Distributed Max. 8192 bytes
I/O process image 256/256
Digital channels 65536/65536
Of those central Max. 1024
Analog channels 4096/4096
Of those central 256/256
Assembly
Racks Max. 4
Modules per rack 8
Number of DP masters
• Integrated
2
• via CP
4
Number of function modules and communication processors you can operate
• FM
Maximum 8
• CP (PtP)
Maximum 8
• CP (LAN)
Maximum 10
Time-of-day
Real-time clock Yes (HW clock)
• Buffered
Yes
• Buffered period
Typically 6 weeks (at an ambient temperature of
104 °F)
• Behavior of the clock on expiration of the
buffered period
The clock keeps running, continuing at the time-
of-day it had when power was switched off.
• Accuracy
Deviation per day: < 10 s
Operating hours counter 4
• Number
0 to 3
• Value range
2
31
hours
(if SFC 101 is used)
• Granularity
1 hour
• Retentive
yes; must be manually restarted after every
restart
Clock synchronization Yes
• In the PLC
Master/slave
• On MPI
Master/slave
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