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Provides a high-level overview of the EFM8UB3 family and its features.
Details the device's power consumption control through peripheral enabling/disabling and power modes.
Describes the multi-purpose I/O pins, port control block features, and digital/analog functions.
Explains how the CPU core and peripherals are clocked by internal and external oscillator resources.
Details the Programmable Counter Array (PCA) module, its channels, and operational modes.
Describes the two 16-bit counter/timers and four 16-bit auto-reload timers, including their features and modes.
Explains the programmable watchdog timer, its function, and features to prevent system malfunction.
Details peripherals like USB0, UART1, SPI0, SMBus, CRC, and CLUs.
Covers the 12-Bit ADC0 and Low Current Comparators (CMP0, CMP1) and their features.
Lists and describes the various reset sources available on the device.
Explains the on-chip Silicon Labs 2-Wire (C2) debug interface for programming and debugging.
Details the memory organization of program memory and data memory spaces.
Describes the memory organization of program memory and data memory spaces.
Details the CIP-51 core's 64 KB program memory space, including flash security.
Explains the internal RAM and XRAM areas, total RAM variation, and memory map.
Presents the flash memory map for 40 KB devices.
Details the EMI0CN register for external memory interface control.
Explains the structure and access methods for Special Function Registers (SFRs).
Explains access methods, bit-addressable SFRs, and the concept of SFR paging.
Provides a memory map of all Special Function Registers by address.
Covers registers for controlling SFR page access, including SFRPAGE and SFRPGCN.
Details the on-chip flash memory for program code and non-volatile data storage.
Introduces the on-chip flash memory, its organization, and programming methods.
Lists the key features of the flash memory, including size, programmability, and security.
Explains flash memory security options, programming, and write/erase precautions.
Details flash memory protection options against accidental modification and unauthorized access.
Describes procedures for writing and erasing flash memory bytes and pages.
Explains the lock and key function for flash erasures and writes using the FLKEY register.
Provides a step-by-step procedure for erasing a page of flash memory using firmware.
Details the procedure for writing a single byte of flash memory using firmware.
Provides guidelines to prevent accidental flash modification by firmware.
Covers registers for controlling flash memory operations, including PSCTL and FLKEY.
Details the PSCTL register for enabling program store erase and write operations.
Explains the FLKEY register for flash lock and key functions for erasures and writes.
Explains how to identify the device family, derivative, and revision using SFRs.
Describes SFRs used to identify device capabilities at runtime.
Discusses the 128-bit universally unique identifier (UUID) pre-programmed into devices.
Covers registers for device identification: DEVICEID, DERIVID, and REVID.
Details the DEVICEID register, which returns the 8-bit device ID.
Explains the DERIVID register for identifying the device derivative and its revision letter.
Describes the REVID register, which returns the 8-bit revision ID.
Details the extended interrupt system, sources, vectors, priorities, and latency.
Introduces the interrupt system supporting multiple sources and priority levels.
Explains interrupt sources, vectors, and the interrupt priority decoding table.
Describes how interrupt sources can be programmed to one of four priority levels.
Explains how interrupt response time depends on CPU state and priority.
Provides a summary table of interrupt sources, vectors, priorities, and pending flags.
Details registers for controlling interrupts, including enable (IE, EIE1, EIE2) and priority (IP, EIP1, EIP2) settings.
Explains the IE register for globally enabling/disabling interrupts and overriding individual mask settings.
Details the IP register for controlling the LSB of interrupt priority levels.
Explains the IPH register for controlling the MSB of interrupt priority levels.
Details the EIE1 register for enabling extended interrupts like Timer, Comparator, PCA, and ADC.
Explains the EIP1 register for setting the LSB of extended interrupt priorities.
Details the EIP1H register for setting the MSB of extended interrupt priorities.
Details the EIE2 register for enabling extended interrupts like CL0, Timer 4, Timer 5, VBUS, and USB0.
Explains the EIP2 register for setting the LSB of extended interrupt priorities.
Details the EIP2H register for setting the MSB of extended interrupt priorities.
Details power management features including power modes and internal regulators.
Provides an overview of how to control device power consumption by enabling/disabling peripherals.
Lists the key power management features of the EFM8UB3 devices.
Details the Idle power mode where CPU execution halts but peripherals remain active.
Explains Stop mode where CPU and peripheral clocks are stopped; terminated by reset.
Describes Suspend mode where internal oscillators halt, entering a low power state.
Explains Snooze mode where internal oscillators halt and LDO enters low-power mode.
Details Shutdown mode where CPU halts and internal LDO powers down.
Describes the 5V-to-3.3V regulator, its voltage regulation, and power modes.
Covers registers for controlling power management, including PCON0, PCON1, PSTAT0, REG0CN, REG1CN.
Details the PCON0 register for selecting power modes like Idle and Stop.
Explains the PCON1 register for controlling Snooze and Suspend modes.
Describes the PSTAT0 register for reporting power status and wake-up events.
Details the REG0CN register for controlling the voltage regulator's behavior in stop and shutdown modes.
Explains the REG1CN register for controlling the 5V regulator's bias, suspend, and enable settings.
Details the clock control system, including internal and external oscillators.
Introduces clocking and oscillator resources for the CPU core and peripherals.
Lists the features of the clock control system, including internal and external oscillators.
Explains how the clock control system selects clock sources and uses dividers.
Details the CLKSEL register for selecting the system clock source and CLKDIV for the divider.
Covers registers for controlling clocking and oscillators, including CLKSEL, HFO0CAL, HFO1CAL, HFOCN, LFO0CN.
Details the CLKSEL register for selecting the system clock source and divider.
Explains the HFO0CAL register for calibrating the 24.5 MHz internal oscillator.
Details the HFO1CAL register for calibrating the 48 MHz internal oscillator.
Covers the HFOCN register for enabling/disabling high-frequency oscillators.
Details the LFO0CN register for controlling the low-frequency oscillator and its divider.
Explains the device's reset circuitry, including various reset sources and the supply monitor.
Introduces the reset circuitry and its function in placing the controller in a default condition.
Lists the available reset sources on the device.
Describes the events that occur upon entering a reset state and the sequence upon exiting.
Details the events that occur upon entering any reset state.
Explains the Power-On Reset (POR) circuit and its timing during power-up.
Describes the supply monitor's function to detect voltage drops and generate a reset.
Explains the use of the external RSTb pin for forcing a reset.
Details the Missing Clock Detector (MCD) reset functionality triggered by clock loss.
Explains how Comparator 0 can be configured as a reset source.
Describes how the Watchdog Timer (WDT) can generate a reset upon malfunction.
Explains resets generated due to illegal flash access or security setting violations.
Details how software can force a reset by writing to the SWRSF bit.
Explains how USB0 can be selected as a reset source for system resets.
Covers registers for controlling reset sources and supply monitor settings.
Details the RSTSRC register for indicating the source of the most recent reset.
Explains the VDM0CN register for enabling/disabling the supply monitor circuit.
Introduces the CIP-51 microcontroller core, its architecture, and compatibility.
Introduces the CIP-51 core as a high-speed, pipelined, 8-bit core.
Lists the key features of the CIP-51 core, including architecture, clock frequency, and MIPS.
Explains programming/debugging support, the prefetch engine, and the instruction set.
Details in-system programming and debugging via the C2 interface.
Explains the multi-byte prefetch engine for enabling faster core clock speeds.
Describes the instruction set compatibility with MCS-51 and provides an instruction summary table.
Details the core CPU registers, including Data Pointers, Stack Pointer, Accumulator, B Register, and PSW.
Describes the DPL register, the low byte of the 16-bit DPTR.
Details the DPH register, the high byte of the 16-bit DPTR.
Explains the SP register which holds the location of the top of the stack.
Describes the ACC register, the primary accumulator for arithmetic operations.
Details the B register, serving as a second accumulator for arithmetic operations.
Explains the PSW register containing status flags and register bank select bits.
Details the PFE0CN register for controlling the prefetch engine's flash read timing.
Covers port I/O, crossbar, external interrupts, and port match functionality.
Introduces digital and analog resources available on multi-purpose I/O pins.
Lists the features of the port control block, including I/O pins and crossbar decoder.
Details how port pins are configured as digital or analog I/O using special function registers.
Explains the steps for configuring port pins for digital I/O and analog modes.
Describes how port drive strength is controlled on a port-by-port basis using the PRTDRV register.
Details the mapping of port I/O pins to analog and digital functions.
Shows the mapping of port I/O pins to analog functions like ADC, Comparators, VREF, and AGND.
Displays the potential mapping of port I/O to each digital function via the crossbar.
Explains how the priority crossbar decoder assigns I/O functions to physical pins.
Illustrates the potential peripheral-to-pin assignments available to the crossbar.
Describes the two direct-pin digital interrupt sources (INT0 and INT1).
Explains Port Match functionality for triggering events based on logic value changes on port pins.
Details how to access port I/O pins directly through Special Function Registers.
Covers registers for controlling port I/O behavior, including crossbar, mask, match, and mode registers.
Details the XBR0 register for controlling crossbar assignments for various peripherals.
Explains the XBR1 register for controlling crossbar assignments for Timers and PCA.
Details the XBR2 register for controlling UART1 and weak pull-up settings.
Describes the PRTDRV register for controlling port drive strength settings.
Details the P0MASK register for defining mask values for Port 0 bits in port mismatch events.
Explains the P0MAT register for setting match values for Port 0 bits in port mismatch events.
Details the P0 register, which sets the port latch logic value for Port 0 I/O pins.
Explains the P0MDIN register for configuring Port 0 pins as analog or digital inputs.
Details the P0MDOUT register for configuring Port 0 pins as open-drain or push-pull outputs.
Explains the P0SKIP register for skipping Port 0 pins from crossbar assignments.
Details the P1MASK register for defining mask values for Port 1 bits in port mismatch events.
Explains the P1MAT register for setting match values for Port 1 bits in port mismatch events.
Details the P1 register, which sets the port latch logic value for Port 1 I/O pins.
Explains the P1MDIN register for configuring Port 1 pins as analog or digital inputs.
Details the P1MDOUT register for configuring Port 1 pins as open-drain or push-pull outputs.
Explains the P1SKIP register for skipping Port 1 pins from crossbar assignments.
Details the P2MASK register for defining mask values for Port 2 bits in port mismatch events.
Explains the P2MAT register for setting match values for Port 2 bits in port mismatch events.
Details the P2 register, which sets the port latch logic value for Port 2 I/O pins.
Explains the P2MDIN register for configuring Port 2 pins as analog or digital inputs.
Details the P2MDOUT register for configuring Port 2 pins as open-drain or push-pull outputs.
Covers registers for configuring INT0 and INT1 interrupts, including polarity and port selection.
Details the IT01CF register for configuring INT0/INT1 polarity and port selection.
Details the SAR ADC with 12-, 10-, and 8-bit modes, track-and-hold, and window detector.
Introduces the ADC, its modes, and voltage reference selection.
Lists the key features of the ADC, including input channels, modes, and triggers.
Explains ADC clocking, voltage references, input selection, gain, and power considerations.
Describes how the ADC is clocked by an adjustable conversion clock (SARCLK).
Details the configurable voltage reference options for the ADC.
Explains the internal voltage reference with two programmable levels.
Describes using the power supply or internal LDO as voltage references.
Details how to apply an external reference voltage to the VREF pin.
Explains the analog ground reference option to prevent ground noise.
Describes the analog multiplexer for selecting ADC input channels.
Provides tables showing ADC0 input multiplexer channel selections.
Details the ADC gain settings of 1x and 0.5x for full-scale reading.
Explains the different methods to initiate ADC conversions: software, hardware, or external pin.
Describes the minimum tracking time required for ADC conversion accuracy.
Explains Burst mode for power saving, allowing ADC to remain in low power state between conversions.
Details how to enable 8-bit mode for faster conversion using fewer SAR clock cycles.
Explains 12-bit mode, which combines four 10-bit conversions for higher resolution.
Describes how the ADC output data can be right-justified or left-justified.
Provides guidelines for optimizing ADC power consumption using burst mode and low power options.
Details the window comparator for continuous output comparison against user-programmed limits.
Explains the on-chip temperature sensor available via the ADC multiplexer input.
Provides steps for calibrating the temperature sensor for absolute measurements.
Covers registers for controlling ADC0 operation, including enable, mode, and configuration.
Details the ADC0CN0 register for ADC enable, burst mode, and interrupt flags.
Explains the ADC0CN1 register for selecting the start of conversion source and common mode buffer.
Details the ADC0CF register for SAR clock divider, 8-bit mode, track mode, and gain control.
Explains the ADC0AC register for 12-bit mode, accumulate enable, shift, and repeat count.
Details the ADC0PWR register for bias power select, mux/reference low power, and burst mode power up time.
Explains the ADC0TK register for 12-bit sampling mode and burst mode tracking time.
Details the ADC0H register for the most significant byte of the 16-bit ADC0 accumulator.
Explains the ADC0L register for the least significant byte of the 16-bit ADC0 accumulator.
Details the ADC0GTH register for the greater-than window compare.
Explains the ADC0GTL register for the greater-than window compare.
Details the ADC0LTH register for the less-than window compare.
Explains the ADC0LTL register for the less-than window compare.
Details the ADC0MX register for selecting the positive input channel for ADC0.
Explains the REF0CN register for selecting internal/external references and ground.
Covers the CMP0 and CMP1 analog comparators, their features, and control registers.
Introduces analog comparators for comparing two analog inputs.
Lists the features of the comparators, including input options, hysteresis, and response time.
Explains comparator response time, hysteresis, input selection, and output routing.
Details the trade-off between comparator response time and supply current.
Explains how comparator hysteresis is software-programmable.
Describes how comparator inputs are routed to port pins or internal signals.
Provides tables for selecting multiplexer channels for CMP0 and CMP1 inputs.
Details the comparator's dedicated reference DAC and its connection configurations.
Explains how comparator outputs can be routed to port pins or generate interrupts.
Describes how the output state of the comparator can be inverted using the CPINV bit.
Explains the feature to inhibit output changes when PCA's CEX2 channel is low.
Covers CMP0 control registers, including CMP0CN0, CMP0MD, CMP0MX, and CMP0CN1.
Details the CMP0CN0 register for comparator enable, output state, and edge interrupts.
Explains the CMP0MD register for selecting comparator mode and input connection.
Details the CMP0MX register for selecting negative and positive input multiplexers.
Explains the CMP0CN1 register for output inhibit and internal DAC reference level control.
Covers CMP1 control registers, including CMP1CN0, CMP1MD, CMP1MX, and CMP1CN1.
Details the CMP1CN0 register for comparator enable, output state, and edge interrupts.
Explains the CMP1MD register for selecting comparator mode and input connection.
Details the CMP1MX register for selecting negative and positive input multiplexers.
Explains the CMP1CN1 register for output inhibit and internal DAC reference level control.
Details the CLU module with four independent units for user-programmable digital logic.
Introduces the configurable logic (CL) module for user-programmed digital logic.
Lists the key features of the Configurable Logic block, including units, functions, and operations.
Explains CLU configuration sequence, input multiplexer selection, and output configuration.
Outlines the general steps for configuring CLUs before enabling them.
Describes selecting inputs for the CLU's LUT using MXA, MXB, and carry inputs.
Provides tables showing CLUnA and CLUnB input selections.
Explains how CLU outputs can be asynchronous or synchronous, and routed to pins.
Details how the boolean logic function in each CLU is determined by the LUT and FNSEL field.
Covers registers for controlling CLUs, including enable (CLEN0, CLIE0), flags (CLIF0), and output (CLOUT0).
Details the CLEN0 register for enabling CLU0, CLU1, CLU2, and CLU3.
Explains the CLIE0 register for enabling interrupts based on CLU rising/falling edges.
Details the CLIF0 register, which holds interrupt flags for CLU rising/falling edges.
Explains the CLOUT0 register for accessing the logic level of CLU outputs.
Details the CLU0MX register for selecting A and B inputs to CLU0.
Explains the CLU0FN register for selecting the LUT function for CLU0.
Details the CLU0CF register for output select, port enable, reset, and clock selection.
Details the CLU1MX register for selecting A and B inputs to CLU1.
Explains the CLU1FN register for selecting the LUT function for CLU1.
Details the CLU1CF register for output select, port enable, reset, and clock selection.
Details the CLU2MX register for selecting A and B inputs to CLU2.
Explains the CLU2FN register for selecting the LUT function for CLU2.
Details the CLU2CF register for output select, port enable, reset, and clock selection.
Details the CLU3MX register for selecting A and B inputs to CLU3.
Explains the CLU3FN register for selecting the LUT function for CLU3.
Details the CLU3CF register for output select, port enable, reset, and clock selection.
Details the CRC0 module for hardware calculations of CRC, flash verification, and protocols.
Introduces the CRC module for performing CRC using a 16-bit polynomial.
Lists CRC module features: CCITT-16 polynomial, bit reversal, and flash CRC calculation.
Explains the 16-bit CRC algorithm, its usage on data streams, and code memory checking.
Describes the algorithm for generating a 16-bit CRC result.
Explains how to perform CRC calculations on arbitrary data sets using the CRC module.
Details how to configure the CRC module for automatic CRC calculation on code memory blocks.
Explains the hardware feature to reverse the bit order of each byte in CRC0.
Covers registers for controlling CRC0 operation, including CRC0CN0, CRC0IN, CRC0DAT, CRC0ST, CRC0CNT, CRC0FLIP, CRC0CN1.
Details the CRC0CN0 register for CRC initialization and result pointer selection.
Explains the CRC0IN register for inputting data bytes into the CRC algorithm.
Details the CRC0DAT register for outputting the CRC result.
Explains the CRC0ST register for specifying the flash block to start automatic CRC calculation.
Details the CRC0CNT register for specifying the number of flash blocks for automatic CRC calculation.
Explains the CRC0FLIP register for performing bit reversal on data.
Details the CRC0CN1 register for enabling automatic CRC calculation.
Details the PCA0 module, providing timer and PWM functionality with multiple channels.
Introduces the PCA module, offering enhanced timer and PWM functionality.
Lists the key features of the PCA, including time base, channels, and operational modes.
Explains PCA counter/timer operation, interrupt sources, and capture/compare modules.
Details the 16-bit PCA counter/timer, its SFRs, and timebase input options.
Explains the PCA0 module's interrupt vector and how event flags generate interrupts.
Describes how capture/compare modules operate independently in various modes.
Explains how the output polarity of each PCA channel is selectable.
Details edge-triggered capture mode for measuring system events against the clock source.
Explains Software Timer mode where the PCA counter/timer is compared to a capture/compare register.
Describes High-Speed Output mode where the CEXn pin is toggled on PCA match.
Explains Frequency Output mode for generating programmable-frequency square waves.
Details PWM waveform generation with edge- or center-aligned modes and resolutions.
Details edge-aligned mode, including edge transitions, polarity, and match/overflow edges.
Describes center-aligned mode, including edge transitions, polarity, and center points.
Explains 8-bit and 9- to 11-bit PWM modes, including cycle length and auto-reload register usage.
Details how to operate a PCA module in 16-Bit PWM mode.
Explains the comparator clear function for utilizing Comparator 0 output to clear CEXn.
Covers registers for controlling PCA0, including PCA0CN0, PCA0MD, PCA0PWM, PCA0CLR, PCA0L, PCA0H, PCA0POL, PCA0CENT.
Details the PCA0CN0 register for PCA counter/timer run control and overflow flags.
Explains the PCA0MD register for selecting PCA counter timebase and overflow interrupt.
Details the PCA0PWM register for selecting PWM cycle length and auto-reload options.
Explains the PCA0CLR register for configuring comparator clear polarity and select.
Details the PCA0L register holding the low byte (LSB) of the 16-bit PCA Counter/Timer.
Explains the PCA0H register holding the high byte (MSB) of the 16-bit PCA Counter/Timer.
Details the PCA0POL register for selecting the polarity of PCA output channels.
Explains the PCA0CENT register for selecting center alignment properties for PWM modes.
Details the PCA0CPM0 register for configuring Channel 0 mode, including PWM and capture.
Explains the PCA0CPL0 register holding the low byte for Channel 0 capture/compare.
Details the PCA0CPH0 register holding the high byte for Channel 0 capture/compare.
Details the PCA0CPM1 register for configuring Channel 1 mode, including PWM and capture.
Explains the PCA0CPL1 register holding the low byte for Channel 1 capture/compare.
Details the PCA0CPH1 register holding the high byte for Channel 1 capture/compare.
Details the PCA0CPM2 register for configuring Channel 2 mode, including PWM and capture.
Explains the PCA0CPL2 register holding the low byte for Channel 2 capture/compare.
Details the PCA0CPH2 register holding the high byte for Channel 2 capture/compare.
Details the SPI0 module for flexible, full-duplex synchronous serial bus communication.
Introduces the SPI module for master/slave serial bus communication.
Lists SPI features like master/slave modes, clock frequencies, and FIFO support.
Explains SPI signals, master/slave operation, and data transfer methods.
Details the SPI interface signals: MOSI, MISO, SCK, and NSS, and their roles in master/slave modes.
Explains how SPI signals can be routed through the crossbar or from CLU outputs.
Describes how an SPI master device initiates data transfers, controls speed, and uses the transmit buffer.
Explains how the SPI block operates as a slave, shifting bytes and using the receive buffer.
Details how clock phase and polarity are selected using SPInCFG register bits.
Explains byte-by-byte SPI data transfer using SPInDAT register and SPIF flag.
Describes the implementation of independent two-byte FIFOs for transmit and receive paths.
Provides timing diagrams for SPI master and slave modes.
Covers registers for SPI0 configuration and control, including SPI0CFG, SPI0CN0, SPI0CKR, SPI0DAT, SPI0FCN0, SPI0FCN1, SPI0FCT, SPI0PCF.
Details the SPI0CFG register for configuring SPI0 operation mode, clock phase, and polarity.
Explains the SPI0CN0 register for SPI interrupt flag, write collision, mode fault, and overrun flags.
Details the SPI0CKR register for determining the SCK output frequency in master mode.
Explains the SPI0DAT register used for transmitting and receiving SPI0 data.
Details the SPI0FCN0 register for transmit FIFO request and threshold settings.
Explains the SPI0FCN1 register for transmit hold, interrupt enables, and receive FIFO threshold.
Details the SPI0FCT register indicating the number of bytes in the transmit and receive FIFOs.
Explains the SPI0PCF register for selecting clock, MISO, and MOSI sources.
Details the SMBus interface, its features, protocol, and configuration.
Introduces the SMBus interface as a two-wire, bi-directional serial bus.
Lists SMBus features like transfer speeds, modes, arbitration, and FIFO support.
Explains SMBus protocol, supporting documents, configuration, and operational modes.
Describes the SMBus protocol, voltage levels, arbitration, and clock timing.
Explains how to configure the SMBus module for master/slave modes and serial transfers.
Details the four operational modes: Master Transmitter, Master Receiver, Slave Transmitter, Slave Receiver.
Covers SMB0 control registers, including SMB0CF, SMB0TC, SMB0CN0, SMB0ADR, SMB0ADM, SMB0DAT, SMB0FCN0, SMB0FCN1, SMB0RXLN, SMB0FCT.
Details the SMB0CF register for SMBus enable, slave inhibit, busy indicator, and clock source selection.
Explains the SMB0TC register for SMBus pin swap and setup/hold delay extension.
Details the SMB0CN0 register for master/slave indicator, transmit mode, start/stop flags, and ACK control.
Explains the SMB0ADR register for defining hardware slave addresses and general call enable.
Details the SMB0ADM register for defining the slave address mask for hardware recognition.
Explains the SMB0DAT register used to access the TX and RX FIFOs.
Details the SMB0FCN0 register for transmit/receive FIFO request and threshold settings.
Explains the SMB0FCN1 register for transmit hold, FIFO enable, and receive FIFO settings.
Details the SMB0RXLN register for setting the number of bytes to receive.
Explains the SMB0FCT register indicating the number of bytes in the transmit and receive FIFOs.
Details the six counter/timers, their modes, features, and system connections.
Introduces the six counter/timers, their compatibility with 8051, and modes of operation.
Lists features of Timer 0/1 and Timer 2-5, including modes, clock sources, and capture capabilities.
Explains timer system connections, operational modes, and chaining capabilities.
Details how timers connect to other peripherals and trigger system events.
Describes Timer 0 and Timer 1 implementation, control registers, and operating modes.
Explains the operational modes for Timer 0 and Timer 1: 13-bit, 16-bit, 8-bit auto-reload, and 8-bit split.
Details the configuration and operation of Timer 0/1 in 13-bit counter/timer mode.
Explains Mode 1 operation, which uses all 16 bits of the counter/timer registers.
Describes Mode 2 configuration for 8-bit counter/timers with automatic reload.
Explains Mode 3 where Timer 0 is configured as two separate 8-bit counter/timers.
Describes Timer 2-5 as functionally equivalent 16-bit timers with auto-reload and capture modes.
Details the 16-bit timer operation with auto-reload.
Explains the 8-bit timers operation in split mode with auto-reload.
Describes Capture mode for measuring system events against a selected clock source.
Explains chaining Timer 3 and Timer 4 for longer counters or wake source functionality.
Covers registers for controlling timer clock sources and modes, including CKCON0, CKCON1, TCON, TMOD.
Details the CKCON0 register for selecting clock sources for Timers 1, 2, and 3.
Explains the CKCON1 register for selecting clock sources for Timers 4 and 5.
Details the TCON register for Timer 0/1 control, overflow flags, and interrupt types.
Explains the TMOD register for selecting Timer 0/1 operation modes.
Details the TL0 register holding the low byte of the 16-bit Timer 0.
Explains the TL1 register holding the low byte of the 16-bit Timer 1.
Details the TH0 register holding the high byte of the 16-bit Timer 0.
Explains the TH1 register holding the high byte of the 16-bit Timer 1.
Details the TMR2CN0 register for Timer 2 overflow flags, run control, and clock select.
Explains the TMR2RLL register holding the reload value for Timer 2 low byte.
Details the TMR2RLH register holding the reload value for Timer 2 high byte.
Explains the TMR2L register containing the low byte of the 16-bit Timer 2.
Details the TMR2H register containing the high byte of the 16-bit Timer 2.
Explains the TMR3CN1 register for force reload select and capture select.
Details the TMR3CN0 register for Timer 3 overflow flags, run control, and clock select.
Explains the TMR3RLL register holding the reload value for Timer 3 low byte.
Details the TMR3RLH register holding the reload value for Timer 3 high byte.
Explains the TMR3L register containing the low byte of the 16-bit Timer 3.
Details the TMR3H register containing the high byte of the 16-bit Timer 3.
Explains the TMR3CN1 register for force reload select and capture select.
Details the TMR4CN0 register for Timer 4 overflow flags, run control, and clock select.
Explains the TMR4RLL register holding the reload value for Timer 4 low byte.
Details the TMR4RLH register holding the reload value for Timer 4 high byte.
Explains the TMR4L register containing the low byte of the 16-bit Timer 4.
Details the TMR4H register containing the high byte of the 16-bit Timer 4.
Explains the TMR4CN1 register for force reload select and capture select.
Explains the TMR5RLL register holding the reload value for Timer 5 low byte.
Details the TMR5RLH register holding the reload value for Timer 5 high byte.
Explains the TMR5L register containing the low byte of the 16-bit Timer 5.
Details the TMR5H register containing the high byte of the 16-bit Timer 5.
Details the TMR5CN0 register for Timer 5 overflow flags, run control, and clock select.
Explains the TMR5CN1 register for force reload select and capture select.
Details the UART1 serial port, its features, baud rate generation, and data formatting.
Introduces UART1 as an asynchronous, full duplex serial port with baud rate generation.
Lists UART1 features such as asynchronous transmission, baud rate generation, and FIFO support.
Explains UART1 baud rate generation, data format, flow control, and FIFO data transfer.
Details the dedicated 16-bit timer and prescaler for generating UART1 baud rates.
Describes UART1 data formatting options: start bit, data bits, parity, and stop bits.
Explains hardware flow control using CTS and RTS pins.
Describes standard asynchronous, full duplex communication via SBUF1 register.
Explains UART1's receive and transmit buffers to reduce interrupt overhead.
Details multiprocessor communication using the extra data bit and address byte.
Explains UART1's LIN features like break detection and baud rate adjustment.
Describes automatic baud rate detection and adjustment supported by the UART.
Explains how the RX input of UART1 can be routed through the crossbar to CLU outputs.
Covers registers for controlling UART1 operation, including SCON1, SMOD1, SBUF1, SBCON1, SBRLH1, SBRLL1, UART1FCN0, UART1FCN1, UART1FCT, UART1LIN, UART1PCF.
Details the SCON1 register for UART1 control, including overrun, parity, and receiver enable flags.
Explains the SMOD1 register for multiprocessor communication, parity, data length, and extra bit enable.
Details the SBUF1 register for accessing the transmit and receive FIFOs.
Explains the SBCON1 register for enabling the baud rate generator and selecting prescaler.
Details the SBRLH1 register holding the high byte of the UART1 baud rate generator.
Explains the SBRLL1 register holding the low byte of the UART1 baud rate generator.
Details the UART1FCN0 register for transmit FIFO request and threshold settings.
Explains the UART1FCN1 register for transmit hold, interrupt enables, and receive FIFO settings.
Details the UART1FCT register indicating the number of bytes in the transmit and receive FIFOs.
Explains the UART1LIN register for LIN mode, break detection, and autobaud settings.
Details the UART1PCF register for selecting the RX source.
Details the USB0 peripheral, its features, block diagram, and endpoints.
Introduces the USB0 peripheral as a full-speed USB 2.0 compliant device controller.
Lists USB0 features like full/low speed, endpoints, low energy mode, and charger detection.
Explains endpoint addressing, transceiver control, clock configuration, VBUS control, registers, FIFO management, function addressing, and interrupts.
Details the eight endpoint pipes and their associated USB protocol addresses.
Explains transceiver configuration via USB0XCN for enable, speed, and test modes.
Describes USB module clock configuration for full or low speed operation.
Explains VBUS control for detecting host connection and generating system interrupts.
Details indirect register access via USB0ADR and USB0DAT SFRs.
Explains the 1024 bytes of on-chip XRAM used as FIFO space for USB block.
Describes the FADDR register for holding the current USB function address.
Explains USB register POWER for USB block control: reset, suspend, resume, and enable.
Details USB interrupt flags and enable bits located in IN1INT, OUT1INT, CMINT, IN1IE, OUT1IE, CMIE registers.
Explains the SIE for performing low-level USB protocol tasks and interrupting the processor.
Describes Endpoint 0 management through E0CSR, E0CNT, and its transactions.
Details configuration and control registers for Endpoints 1-3 (IN, OUT, Split Mode).
Explains USB module controls for optimizing power usage based on bus activity.
Details the USB charger detection circuit compliant with USB-IF Battery Charging Specification.
Covers USB0 control registers, including transceiver control, address, data, endpoint index, and clock recovery.
Details the USB0XCN register for transceiver control: enable, speed, and test modes.
Explains the USB0ADR register for selecting USB0 registers via indirect access.
Details the USB0DAT register used for indirectly reading and writing USB0 registers.
Explains the INDEX register for selecting the target endpoint for indexed USB0 register access.
Details the CLKREC register for USB clock recovery control.
Explains the FIFODATA register for accessing the Endpoint 0 FIFO.
Details the FIFODATA register for accessing the Endpoint 1 FIFO.
Explains the FIFODATA register for accessing the Endpoint 2 FIFO.
Details the FIFODATA register for accessing the Endpoint 3 FIFO.
Explains the FADDR register for holding the current USB function address.
Details the POWER register for USB0 power control: suspend, resume, and reset.
Explains the FRAMEL register containing bits 7-0 of the last received frame number.
Details the FRAMEH register containing bits 10-8 of the last received frame number.
Explains the IN1INT register for IN endpoint interrupt flags.
Details the OUT1INT register for OUT endpoint interrupt flags.
Explains the CMINT register for common USB interrupt flags like SOF, Reset, Resume, Suspend.
Details the IN1IE register for enabling IN endpoint interrupts.
Explains the OUT1IE register for enabling OUT endpoint interrupts.
Details the CMIE register for enabling common USB interrupts.
Explains the E0CSR register for Endpoint 0 control: setup, stall, and packet status.
Details the E0CNT register for the number of received data bytes in Endpoint 0 FIFO.
Explains the EENABLE register for enabling or disabling Endpoints 1-3.
Details the EINCSRL register for IN endpoint control: data toggle, stall, flush, and packet status.
Explains the EINCSRH register for IN endpoint control: double-buffer, isochronous, and direction select.
Details the EOUTCSRL register for OUT endpoint control: stall, FIFO flush, and packet status.
Explains the EOUTCSRH register for OUT endpoint control: double-buffer and isochronous transfer enable.
Details the EOUTCNTL register holding the lower bits of the data byte count.
Explains the EOUTCNTH register holding the upper bits of the data byte count.
Details the USB0CF register for VBUS control and USB0 clock source selection.
Explains the USB0AEC register for low energy mode status and control.
Details the USB0CDCF register for configuring charger detection features and interrupts.
Explains the USB0CDCN register for enabling charger detection, secondary, and primary detection.
Details the USB0CDSTA register for reporting charger detection status.
Details the programmable watchdog timer (WDT0) and its control register.
Introduces the watchdog timer (WDT) that runs off the low-frequency oscillator.
Lists watchdog timer features: programmable timeout, low-frequency oscillator, and lock-out.
Explains how to enable, reset, disable, and set the watchdog timer interval.
Covers the WDT0 control register, WDTCN.
Details the WDTCN register for controlling the watchdog timer's behavior.
Details the C2 debug interface for flash programming and in-system debugging.
Introduces the on-chip Silicon Labs 2-Wire (C2) debug interface.
Lists C2 interface features: programming, debugging, non-intrusive, memory access, breakpoints.
Explains how C2 pins can be shared with user functions for debugging and programming.
Covers C2 interface registers: C2ADD, C2DEVID, C2REVID, C2FPCTL, C2FPDAT.
Details the C2ADD register for selecting target data registers for C2 commands.
Explains the C2DEVID register returning the 8-bit device ID.
Details the C2REVID register returning the 8-bit revision ID.
Explains the C2FPCTL register for enabling flash programming via the C2 interface.
Details the C2FPDAT register for passing flash commands, addresses, and data.
Provides revision history for the document, detailing changes in each version.
Details updates made in Revision 0.2, including WDT diagram and sections.
Notes the initial release of the document.
General| Operating Temperature | -40 °C to +85 °C |
|---|---|
| Core | 8051 |
| Flash Memory | Up to 64KB |
| RAM | Up to 4KB |
| Clock Speed | Up to 72MHz |
| ADC Resolution | 10-bit to 12-bit |
| Communication Interfaces | I2C, SPI, UART |
| DAC Resolution | 12-bit |
| Timers | 16-bit |
| Package Options | QFN, TSSOP |
| Number of DAC Channels | Up to 2 |
