Sony CDP-497 - SECTION 4 DIAGRAMS; Integrated Circuit Pin Functions

CDP-497
SECTION
4
DIAGRAMS
4-1. PIN
FUNCTIONS
•
IC101
(CXD2501Q)
PIN
FUNCTION
I/O
Function
ADII
I
A/D
signal
input.
2
ADIO
0
Analog switch
output.
3
RF
I
RF signal
input.
4
TE
I
Tracking
error
signal
input.
5
SE
I
SE
signal input.
6
NC
Not used.
7
FE
I
Focus
error
signal
input.
8
VC
n
Center
voltage
(2.5V)
input.
9
DVSS
Digital GND.
10
NC
Not used.
11
ATSK
12
NC
13
DFSW
I
Prevents the DFCT
circuit from operating
at
“H”.
14
DFCT
0
DFCT signal
output.
15
XTAL
I
Master clock
signal input.
16
NC
Not used.
17
XTSL
Frequency switching
of
input master clock
signal.
22
MHz
at “H”. 1 1 MHz at “L”.
18
UOCK
I
Lock signal
input.
19
FOK
0
Focus
OK
signal output.
20
MIRR
0
Mirror
signal
output.
21
CLK
I Clock
signal when transmitting
data from
micro processor.
22
NC
Not
used.
23
I
Latch signal when
transmitting
data from micro processor.
24
I Data
from micro processor.
25
1^^3111
0
Track
jump number count
signal
output.
26
Not used.
DVdd
Digital
+5V.
-
NC
Not used.
[fiQm
SENS 0
SENS
signal output.
SCLK
I
Serial data reading clock.
31
NC
Not
used.
32
DIRC
I DIRC
signal input.
33
XRST
I Reset signal
input.
34
SOCK
Not used.
35 XOLT
36 SOUT
37 NC
SFDR 0
Sled
drive
signal output (FWD).
39
SRON
Not used.
40
SRDR 0
Sled
drive signal output
(REVERSE).
41
SFON
Not used.
42 NC
43
DVSS
Digital
GND.
44
NC
Not
used.