Sony CDP-497 - Board Locations and System Block Diagram

CDP-497 CDP-497
Pin
No.
Pin Name I/O
Function
46
DA04 0
DA04
output
when PSSL=1.
MNT3 output when
PSSL=0.
47
DA03 0
DA03
output
when PSSL=1.
MNT2
output when
PSSL=0.
48
DA02
0
DA02
output
when PSSL=1 .
MNTl
output when
PSSL=0.
49
DAOl
0
DAOl
output
when PSSL=1.
MNTO
output when
PSSL=0.
50
APTR 0
Aperture
correction control
output.
H when Rch.
51
APTL 0
Aperture
correction control
output.
H when Lxh.
52
Vss
GND
53
XTAI
I
16.9344 MHz
crystal
oscillation circuit
input.
Or
33.8688 MHz
input.
54
XTAO 0
16.9344 MHz
crystal
oscillation circuit
input.
55
XTSL
I
Crystal
selection
input
pin. Set
to
L
when
crystal
is
16.9344
MHz.
Set to
H
when 33.8688 MHz.
56
FSTT
0 2/3
frequency
division
output of Pins
®)
and
@
.
Will
not change
by
variable
pitch.
57
C4M
0
4.2336
MHz
output.
Varies simultaneously
with
pitch.
58
C16M 0
16.9344
MHz
output.
Varies simultaneously with
pitch.
59
MD2 I
Digital-Out ON/OFF
control.
ON
at
H, OFF
at
L.
60
DOUT 0
Digital-Out
output pin.
61
EMPH 0
Outputs H if
emphasis
is
present
in the playback
disc. Outputs L
when it is
absent.
62
WFCK 0
WFCK
(Write
Frame
Clock) output.
63
SCOR
0
Outputs H
when
either
sub-code
sync
SO or
SI
has been detected.
64
SBSO 0
SubP
to
W serial
output.
65
EXCK
I SBSO
read-out
clock
input.
66
SQSO
0
SubQ
80 bit and
PCM
peak level data 16
bit
output.
67
SQCK
I SQSO
read-out clock
input.
68
MUTE
I
Mute
at H,
release
at
L.
69
SENS
—
SENS
output.
Outputs to
CPU.
70
XRST I
System
reset.
Resets
at
“L”.
71
DATA
I
Serial
data input
from CPU.
72
XLAT
I
Latch
input from CPU.
Latches
the
serial data
at falling.
73
Vdd
Power supply
(+5V).
74
CLOK
I
Serial
data
transmission
clock input from
CPU.
75
SEIN
I SENS
input
from
SSP.
76
CNIN
I
Track
jump number
count
signal
input.
77
DATO
0
Outputs the serial
data
to
SSP.
78
XLTO
0
Outputs the
serial
data
latch to
SSP. Latches at
falling.
79
CLKO 0
Outputs
the
serial data
transmission clock
to
SSP.
80
MIRR
I Mirror
signal
input.
Uses for a jump above
128 track
with
auto
sequencer.
1,
0
4-2.
CIRCUIT
BOARDS LOCATION
[AEP,
G, UK MODEL]
BD
BOARD
[US,
Canadian,
E,
Australian
MODEL]
BD BOARD
4-3.
BLOCK
DIAGRAM
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11
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12
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