Sony CDX-GT303MP - Schematic Diagram -Main Section (3;3)

CDX-GT25MPW/GT30MP/GT250MP/GT257ME/GT300MP/GT303MP
CDX-GT25MPW/GT30MP/GT250MP/GT257ME/GT300MP/GT303MP
2121
8
J
D
121
C
A
G
B
103 145
I
11
F
742 9
E
136
H
(1/3)
MAIN
2
BOARD
(2/3)
BOARD
3
MAIN
A
BOARD
CN001
KEY
3
IC B/D
IC B/D
4.14.1
0
0
0
0
0
0
0
00
0
0
0
3(3.3)
6
6
3.8(5)
3.6
0.4(2)
3.8
3.8
0.2(1.8)
8.3
3.1(2.9)
3.1(2.9)
0.2(4.2)
0(1.3)
3.8
3.8
3.8
3.8
3.4
3.4
3.4
4.14.1
0
0
4.1
4.1
4.1
4.1
4.1
4.1
8.3
3
3
3.7
3(3.3)
3.4
6.9
8.3
5.6
3.6
2.1
0
0
1.2
8.3
8.3
*
2
*
1
(GT30MP/GT300MP/GT303MP)
(GT25MPW/GT250MP/GT257ME)
(RU MODEL)
(GT30MP/GT300MP/GT303MP)
EXCEPT
US,CND MODEL
US,CND
MODEL
EXCEPT
US,CND MODEL
US,CND
MODEL
GT30MP/GT300MP/GT303MP
GT30MP/GT300MP/GT303MP
*
2
*
1
MAIN BOARD (3/3)
IC302
IC001
50V10C106
40
39
38
37
36
35
34
7
6
5
4
3
2
1
33
32
30
31
8
27
28
29
9
10
11
12
13
14
24 17
25
26
23
22
21
20
19
18
15
16
7
6
5
4
3
2
1
32
30
31
8
27
28
29
9
10
11
12
13
14
24
25
26
23
22
21
20
19
18
17
15
16
BD3447AFV-E2
IC302
ELECTRONIC VOLUME
BUS_RCH
BUS_LCH
TU_RCH
TU_LCH
CD_RCH
CD_LCH
AUX_RCH
AUX_GND
AUX_LCH
EP1
EN
EP2
FP1
FN1
FN2
FP2
EBIAS
DS2_L
DS1_L
DS3_L
DS3_R
DS1_R
DS2_R
EBIAS
NCO
NCO
SA_CLK
SA_DA
SA_OUT
OUT_SLCH
OUT_SRCH
OUT_RLCH
OUT_RRCH
OUT_FLCH
OUT_FRCH
VCC(8.5V)
I2C_SCK
I2C_SIO
GND
FIL
RTAN140M-T111-1
Q102
MUTE
FB15
10V220
C317
100p
C207
50V10C206
50V10C212
220R206
220R106
100p
C107
1kR216
10kR117 10kR107
50V10
C41
RTAN140M-T111-1
Q202
MUTE
1kR112
0.1
C316
R414
0
DRC5114T0L
Q104
MUTE
10kR207
DRC5114T0L
Q103
MUTE
50V10C112
R413 0
50V10C108
1kR116
FB14
10kR217
DRC5114T0L
Q204
MUTE
DRC5114T0L
Q203
MUTE
1kR212 50V10C208
10kR21310kR113
18pC705
470
R151
2.2kR155 12kR153
RKZ18B2KGP1
D719
50V
2.2
C153
18pC707
100pC154
1000pC719
1000pC157
RKZ6.8B2KGP1
D704
UDZSUSTE-176.8B
D153
100pC155
12kR154
18pC708 18pC706
0
L151
470
R152
1000pC709
CAM003
RKZ6.8B2KGP1
D703
C931
1000p 1
C151
1
C152
C812 1 C813 1
0L403
CL051
L101
CN403
15P
3
AUX-LCH
2
KEY-GND
10
SIRCS
13
CLK-LCD
7
RE-1
4
AUX-RCH
14
+B
11
DATA-LCD
1
D-GND
8
KEY-1
5
AUX-GND
15
PANEL
12
CE-LCD
9
KEY-0
6
RE-0
0
C930
JL037
JL038
JL039
JL040
JL041
JL042
JL043
JL044
JL045
JL046
JL047
JL048
JL049
JL050
50V1C203
50V1C103
0.1C26
33p
C8
3.3uH
L1
470k
R2
15p
C6
0.1C27
JW148
FB2
JW147
J1
(ANTENNA)
100R13
R3
470k
R1
0.1C9
0.22C12
22R12
0.01C22
4.7kR11
16V47C28
2pC2
L2
1C21
JW138
0
R16
L3
0.47uH
100R14
12pC18
C3
4p
L6
FM MIX
1
2
34
6
0.1C17
1000pC5
JW137
3.3uHL4
0.1C25
TEF6617T/V1/S470,518
IC001
PHASE LOCKED LOOP(PLL)
AMRFIN
AMRFDEC
FMIN2
FMIN1
GNDRF
VCC2
AMRFAGC
LOUT
ROUT
GNDAUD
AMIFAGC2
MPXIN
MPXOUT
RSSI
XTAL2
XTAL1
GNDD
SCL
SDA
VREF
VREGSUP
VCC1
GND
VCODEC
PLL
PLLREF
TEST
AMSELIN1
AMSELIN2
AMIFAGC1
AMSELOUT1
AMSELOUT2
JW102
1000p
C1
560uHL8
0.01C20
560uHL7
2.2C13
JW126
0
R15
FB1
4MHzX1
0.47C16
0.1C24
0.01C23
VR1
0.01C19
FB3
CAM002
10
11
12
13
14
15
16
18
19
21
22
BUS4
BUS5
BUS7
Mount Mecha
178033131
PL01
XX
J301
2P
1
2
3
L-DA
L-CE
L-CLK
RE-1
NOSE-SW
KEY1
RE-0
SIR
KEY0
CD_RCH CD_LCH
SACLK
SADATA
(CHASSIS)
(CHASSIS)
R
L
REAR/SUB
AUDIO
OUT
J301
2.2μH
R3
100
L2
0
1μH
• See page 17 for waveforms. • See page 24 for IC Block Diagrams.
4-6. SCHEMATIC DIAGRAM – MAIN Section (3/3) –
(Page 23)
(Page 19)
(Page 20)
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