Sony D-EJ119 - Schematic Diagram - Main Board (2;3)

1313
D-EJ119/EJ120/EJ121
D-EJ119/EJ120/EJ121
5-5. SCHEMATIC DIAGRAM – MAIN BOARD (2/3) –
• See page 15 for Waveforms.
R902
R903
R904
C815
R448
R810
R807
C803
R808
R809
C801
C802
CN802
R863
R864
C810
R802
R811
CN801
C812
C813
C811
C814
C809
C806
C805
R841
R832
R830
C804
C807
S802
S803
D803
R804
R845
R827
R833
R838
R813
R805
RB905
RB909
RB913
RB917
R803
R815
C1000
D802
D805
IC801
10k
10k
10k
0.1
0
0
0
0.1
100k
100k
0.1
0.1
24P
22k
22k
0.1
100k
220k
10P
0.01
0.1
470p
0.01
0.01
0.01
0.01
100k
0
0
0.22
0.22
UDZSTE-175.1B
0
0
10k
10k
10k
1k
0
10k
10k
10k
10k
22k
1k
0
MA2ZD14001S0
RSB6.8STE61
T5AW5-5GA5
BUS 1
VCPU
D GND
COMP
D AU GND
VCC2
BATMNT
GND-2
WPSW
BUS 4
BUS 5
COM1
COM2
COM3
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
KEY 1
KEY 2
SCK
SRW
SDTO
SDTI
POWERLT
SCOR
RESET
XWAKEUP
XBUSY
FOK
CLK4M J
GFS
FG
PGM SEL
PGM SEL
PGM SCK
PGM SCK
PGM SDTI
PGM SDTI
PGM SDTO
PGM SDTO
RESET2
RESET2
CLK4M J
CLK4M J
VOL+
VOL-
AMUTE
XRST
POFF
OPSTB
OPGSW
CHGMNT
DCINMNT
HOLD
OPEN
RMKEY
VOL-
VOL+
BEEP
KEY 1
KEY 2
COM0
COM0
COM1
COM2
COM3
SEG0
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
COM
COM
COM
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
COM
0
1
2
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADVREF
AVCPU
SCK
SDTO
SDTI
SRW
XPOWLT
HPSW
SCOR
HP
ACKCD
RESET
XBUSY
FOK
TEST
XOUT
XIN
GND
O
O
I
O
O
O
I
L
I
I
I
I
DSP SEL
VCPU 2V
TEST
NC
TU ON I
VOL+
X4M/16M I
VOL-
LCD REQ O
HOLD I
VDD EEPROM
BEEP O
TUPWR O
WP/XOPEN
AD DCINMNT
WP/AD RMKEY
WP/AD KEY 1
AD BATTMNT
AD KEY 2
AD CHGMNT
AD SEL
V3
V2
V1
C1
C0
RESET TU 0
XRESET O
POFF O
XOPSTBY O
OPGSW O
XWAKEUP O
PGM SDTO
PGM SDTI
CD ON
PGM SCK O
GFS I
FG I
<PGMSEL 0>/SC SEL O
1
5
10
15
20
24
WP/K2 RM
AMUTE 0
SYSTEM
CONTROL
MICOM
TEST
CONNECTOR
C2OPEN 0
EJ120:US, CND, E/EJ121
EJ119/EJ120:EXCEPT US, CND, E
Ver. 1.3