– 28 –
Pin No. Pin Name I/O Function
58 ESP-POWER O
Control signal output to the ESP (Electronic Shock Protection) circuit
59 TRVCTL O
Tracking gain control signal output terminal
60 TRV3 O
61 TRV2 O
62 TRV1 O
63 TRV0 O
64 XSOE O
Serial data output enable signal output to the D-RAM controller (IC680)
65 DSP-SUBQ I
Sub-code Q data signal input from the CXD2545Q (IC601)
66 DSP-SBQCLK O
Sub-code Q data reading clock signal output to the CXD2545Q (IC601)
67 REMOTE I
Sircs remote control signal input from the remote control receiver (IC401)
68 DSP-DATA O
Serial data output to the CXD2545Q (IC601) and D/A converter (IC320)
69 DSP-SENS I
Internal status (SENSE) signal input from the CXD2545Q (IC601)
70 DSP-CLK O
Serial data transfer clock signal output to the CXD2545Q (IC601) and D/A converter (IC320)
71 DSP-SNSCLK O
Sense serial data reading clock signal output to the CXD2545Q (IC601)
72 VDD —
Power supply terminal (+3.3V) (digital system)
73 BEEP O
Beep sound drive signal output terminal
74 C2PO O
C2PO signal control output to the D-RAM controller (IC680) “L”: stop mode, “H”: searching
75 ESP-CLK O
Serial data transfer clock signal output to the D-RAM controller (IC680)
76 ESP-DATA O
Serial data output to the D-RAM controller (IC680)
77 ESP-LT O
Serial data latch pulse signal output to the D-RAM controller (IC680)
78 ESP-SENSE I
Sense serial data input from the D-RAM controller (IC680)
79 XLASERCTL O
Laser diode on/off control signal output to the CXA1791N (IC501) “L”: laser on
80 DSP-SCOR I
Sub-code sync (S0+S1) detection signal input from the CXD2545Q (IC601)
81 OSC1 O
Main system clock output terminal (4.19 MHz)
82 OSC0 I
Main system clock input terminal (4.19 MHz)
83 GND —
Ground terminal (digital system)
84 XT I
Sub system clock input terminal Not used (fixed at “L”)
85 XTO O
Sub system clock output terminal Not used (open)
86 A-SELECT O
Selection signal output to the DATA, BCLK, LRCK signal select switch (IC301)
“L”: CD play, “H”: video CD play
87 XIRCTL O
Power supply on/off control signal for the remote control receiver (IC401) “L”: power on
88 SYS XMT RQ O
Communication request signal output to the MPEG audio/video decoder (IC901)
89 SYS RCV RDY O
Ready signal output to the MPEG audio/video decoder (IC901)
90 MPG XMT RQ I
Communication request signal input from the MPEG audio/video decoder (IC901)
91 ESS-DATAO O
Serial data output to the MPEG audio/video decoder (IC901)
92 ESS-DATAI I
Serial data input from the MPEG audio/video decoder (IC901)
93 ESS-CLK O
Serial data transfer clock signal output to the MPEG audio/video decoder (IC901)
94 RESET I
System reset signal input from the reset signal generator (IC702) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
95 TEST I
Service mode setting terminal The stop status is reset with the falling edge of input signal
“L”: service mode, Normally: “H”
96 DBB CTL2 O
MEGA BASS level control signal output to the BA3574BFS (IC360)
“L”: MEGA BASS level-1, “H”: MEGA BASS level-2
97
VDDL —
98
VDD1 —
99 VDD2 —
100 VDD3 —
Tracking balance control signal output terminal
Power supply output for the liquid crystal display bias
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