Sony D-V8000 - Page 29

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Pin No. Pin Name I/O Function
1 VCC —
Power supply terminal (+3.3V)
2 DRAS B O
Row address strobe signal output to the D-RAM (IC903) “L” active
3 DWE B O
Write enable signal output to the D-RAM (IC903) “L” active
4 MA0 O
5 MA1 O
6 MA2 O
7 MA3 O
8 MA4 O
Address signal output to the D-RAM (IC903)
9 MA5 O
10 MA6 O
11 MA7 O
12 MA8 O
13
DBUS0
I/O
14
DBUS1
I/O
15
DBUS2
I/O
16
DBUS3
I/O
17
DBUS4
I/O
18
DBUS5
I/O
19
DBUS6
I/O
20
DBUS7
I/O
21
DBUS8
I/O
22
DBUS9
I/O
23
DBUS10
I/O
24
DBUS11
I/O
25
DBUS12
I/O
26
DBUS13
I/O
27
DBUS14
I/O
28
DBUS15
I/O
29 RESET B I
Reset signal input from the system controller (IC701) “L”: reset
30 VSS —
Ground terminal
31 VCC —
Power supply terminal (+3.3V)
32 YUV0 O
33 YUV1 O
34 YUV2 O
35 YUV3 O
36 YUV4 O
37 YUV5 O
38 YUV6 O
39 YUV7 O
40 VSSCN B O
Vertical synchronous signal output to the video encoder (IC920)
41 HSSCN B O
Horizontal synchronous signal output to the video encoder (IC920)
42 CLK I
System clock signal input terminal Not used (open)
43 PCLK2XSCN I
System clock signal (27 MHz) input from the video encoder (IC920)
44 PCKLQSCN O
Pixel clock qualifier output for the screen video interface Not used (open)
45 AUX0 O
Sub control signal output terminal Not used (open)
Two-way data bus with the D-RAM (IC903)
Video data output to the video encoder (IC920)
(YUV; Y: luminance signal, UV: Screen video interface chrominance data bus)
• MAIN BOARD (1/2) IC901 ES3210 (MPEG AUDIO/VIDEO DECODER)