Sony FCB-EV7520 - LVDS Receiver Circuit Example (Single Output); LVDS Receiver Circuit Example

Specifications
FCB-EH6500(GB) A-EEP-100-11(1)
60
LVDS receiver circuit example
Sony Corporation is not liable for any damages to user’s hardware incurred by the use of the circuit example shown
below.
LVDS receiver circuit example  (Single output) * Not compatible with 1080p/60, 59.94, 50
DE Y1 Y4
C00 1
10u 25V
HSY N C Y5
C00 8
0.1 u
25V
C6 C3
C00 9
0.1 u
25V
C00 3
0.1 u
25V
CLK
R02 8
10k
FB0 0 3
R02 9
10k
R00 2 100
RXD
C01 0 0.1 u
25V
C00 4
0.1 u
25V
RES E T
C4
D3. 3 V _
TXD
Y7
C0
UNR E G
R00 6 100
C5
R00 3 100 R00 5 100
Y0
CN0 0 1
30P
1TXO U T 4 - 2TXO U T 4 + 3TXO U T 5 - 4TXO U T 5 + 5RES E T 6NC 7TXO U T 6 - 8TXO U T 6 + 9TXO U T 7 -
10TXO U T 7 + 11GND 12GND 13UNR E G 14UNR E G 15UNR E G 16UNR E G 17UNR E G 18RXD 19TXD 20GND 21TXO U T 0 - 22TXO U T 0 + 23TXO U T 1 - 24TXO U T 1 + 25TXO U T 2 - 26TXO U T 2 + 27TXC L K O UT - 28TXC L K O UT + 29TXO U T 3 - 30TXO U T 3 +
C1
FB0 0 2
C00 5
1u
25V
C00 7 0.1 u
25V
R00 1 100
Y2 Y3
R02 7
10k
Y6
C7
IC0 0 1
THC 6 3 L VD 1 0 4 C
1
GND _ 1
2
TES T
3
PD
4
OE
5
R/F
6
RE6
7
RE5
8
RE4
9
VCC _ 9
10
RE3
11
RE2
12
RE1
13
RE0
14
RD6
15
RD5
16
GND _ 1 6
RD4
17
RD3
18
RD2
19
RD1
20
RD0
21
RC6
22
VCC _ 2 3
23
RC5
24
RC4
25
RC3
26
RC2
27
RC1
28
RC0
29
GND _ 3 0
30
CLK O U T
31
RB6
32
33
RB5
34
RB4
35
RB3
36
RB2
37
VCC _ 3 7
38
RB1
39
RB0
40
RA6
41
RA5
42
RA4
43
RA3
44
GND _ 4 4
45
RA2
46
RA1
47
RA0
48
VCC _ 4 8
RA-
49
RA+
50
RB-
51
RB+
52
LVC C
53
RC-
54
RC+
55
RCL K -
56
RCL K +
57
LGN D
58
RD-
59
RD+
60
RE-
61
RE+
62
PGN D
63
PVC C
64
VSY N C
C2
GND
FB0 0 1
R00 4 100
C00 6
1u
25V
C00 2
0.1 u
25V
S00 1
100 Im ped an ce
4 l a n e
3 0 p i n C o a x i a l
• The switch (S001) selects whether to input the rising edge or falling edge of the signal.