Sony ICF-SW1 - Page 10

ICF-SW1
AN-101
CONTROL-
SIGNAL
INPUT
FOR
DIVIDER
OSC
SIGNAL
INPUT
GROUND
ERROR
OUTPUT
ERROR
OUTPUT
Determines the dividing ratio of the fixed-division prescaler.
A 1/4 dividing ratio is made when this terminal is held at “H” (high), and a 1/2 divider is
made when held at “L” (low).
This port is used only when the VCOH terminal (FM in this set) i.e., pin 22 is used.
This set uses this port as a 1/4 divider for FM and 1/2 divider for AM.
Inputs 1/4 divider 10 ~ 130 MHz (0.1 Vp-p MIN.) or 1/2 divider 10 ~ 100 MHz (0.1 Vp-p
MIN.) of local-oscillator output, i.¢., the VCO output. This input signal is connected inter-
nally in this device through the 1/2 fixed-divider prescaler or the 1/4 fixed-divider prescaler
and through the two-module prescaler composed of 1/32 and 1/33 frequency dividers to the
internal programmable counter.
This terminal is pulled down to the ground level when the direct frequency-dividing system
is taken into the circuit or when the Pulse-Swallow system is used with the HF command
executed, i.e., the VCOL (AM) terminal is selected.
A capacitor coupling is needed due to the inclusion of alternate current amplifiers inside this
device.
Receives an AM local-oscillator signals, i.e., the VCO signal from 0.5 MHz to 40 MHz of
0.2 Vp-p minimum.
This port is selected when the direct frequency-dividing system or the Pulse-Swallow system
is used and, at the same time, the HF command is excecuted. These two systems are, how-
ever, different one another as shown below.
INPUT LEVEL INPUT FRE- DIVIDING
DIVIDING SYSTEM (MINIMUM) QUENCY RATIO
|DIRECT 0.1 Vp-p 0.5 to 15 MHz 16 to (217-1)
PULSE-SWALLOW
(HF COMMAND 0.2 Vp-p 0.5 to 40 MHz 1,024 to (2'7-1)
EXECUTED)
This terminal is pulled down to the groung level when the Pulse-Swallow system is used to-
gether with the VHF-command execution, i.e., the VCOH (FM) terminal is selected. A
capacitor coupling is needed due to the inclusion of alternate current amplifiers inside this
chip. Not used.
The ground-return terminal of this device.
Transmits the error signal of the PLL system. When the resultant frequencies obtained by
dividing the local-oscillator frequencies are higher than the reference frequency, an “‘H”
(high)-level signal is output from this port. When these are lower, on the contrary, an ““L”
(low)-level signal is output from this port. When these divided frequencies just coincide with
the reference frequency, this port becomes in a floating state. These output signals from
this port then go through the external lowpass filter to the varactor diodes in the turned
circuits in these frontends of the receiver. The same output waveform as the terminal E01
is obtainable from the next terminal E02, pin 26, and so these two are user-selectable.
When the PLL is disabled, i.e., when the system is set by the PLL commands or the CE
terminal, pin 27, is set to the “‘L”’ (low)-level, these EO1 and EQ2 terminals become in the
floating states.
CHIP
ENABLE
Receives the state-selection signals for this device.
When set a “H” (high), this device works, and vice versa. The PLL section of this device be-
comes forcively in a disabled condition in the duration of wider than 140 wsec of the “L”
(low)-level state. The duration, however, of shorter than 140 usec is not taken into account.
The programmes are using the CKSTP commands. The CKSTP commands are effective only
when the state of this CE is in an “‘L”’ (low) condition. When this CE terminal is in an ‘‘H”’
state, these programmes work like under NOP commands.
When the CKSTP commands are executed when this CE terminal is in an “‘L’’ (low) level,
the internal clock generator and the internal CPU are disabled. In this disabled condition,
the RAM-memory backupings can be made under a very-low current consumption of 3 uA
maximum. In this condition, these display-output signals LCD1 through LCD16 and the
COM1 COM3 become in the off-display mode, i.e., the ‘““L” (low) state.
When the level of this CE terminal is changed from ‘“‘L” to ‘‘H’’, this device is reset and its
programmes start from the location “0” (zero). In this state, the Port A becomes in the
input mode.
Goes to “L”’ (low) when main power switch is OFF or when the power supply is below 1.9V
(1.8 — 2.0 V).