Chapter 5: Configuration, Data, and Status Tags 5-9
Owner’s Guide 0300199-01 Rev. D
GateState[x] 0,1 BOOL
Displays the channel Z state:
0 = Gate is not active.
1 = Gate is active.
CounterInputState[x] 0,1 BOOL
This echoes the state of the input.
NOTE
Note that this is also impacted by the gate and/or enable line.
CountDirection[x] 0,1 BOOL
0 = Counting up.
1 = Counting down.
CTRLimit[x] 0,1 BOOL
This flag is latched when counts are equal to the user-defined limit:
0 = Not set.
1 = Set.
CTRZero[x] 0,1 BOOL
0 = Not set.
1 = Set.
CST DINT
Coordinated System Time. This is the time that the processor reads data from the
FPGA. It is not the actual time that the count occurred. There will only be one
CST tag for the entire module.
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