Tandy 1000 HX - Bus Interface

TANDY COMPUTER PRODUCTS
Equations:
/** Logic Equations **/
disnmi = Inmien # Inmi;
romcs = memr & 'refresh & al9 & al8 & al7 & Iromdis;
bufenb = Imemios & romcs
# memios & fdcack;
bufdir = memr & imio & !fdcack
# memr & Imio & memios
# memr & !mio & ior
# mio & ior
# ior & fdcack & Imemios & Imemr;
System Control Signal Generation
The Timing Control Generator (U20) provides the timing
strobes required by the system. These include LIOW*, LIOR*,
LMEMW*, LMEMR*, LALE, LDEN* and LIO/M*. They are buffered by
U6 and become IOW*
f
IOR*, MEMW*, MEMR*
f
ALE, DEN* and
IO/M*. All external devices, except the 8259A Interrupt
Controller, are buffered by a HCT244 (U6) that is controlled
by the DEN* signal. Since the 8259A is not buffered, the
DEN* signal must remain inactive during access to the 8259A.
The signals LIOW*, LIOR*, LMEMW*, LMEMR*, LALE, LDEN* and
LIO/M* are synthesized 8088 status signals SO*, Si*, S2* and
INTCS* (8259A chip select). See Figure 6.
Bus Specification
Specifications for the bus will include the expansion
connector pin/signal assignments and the signal
characteristics. Refer to the Expansion I/F Connector
diagram. See Figure 7.
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