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TANDY COMPUTER PRODUCTS •
MEGACELL 6845R1 SPECIFICATION DATASHEET FOR 6845 MEGACELL
VE 68C45 MEGACELL DESIGN KIT
CRT CONTROLLER MEGACELL
FEATURES
o Completely integrated with VTI's extensive IC design
tools and libraries
o CMOS (2-micron) M68C45 Megacell configurable as:
— 68C45R
-
CMOS equivalent of Motorola 6845R CRTC
~ 68C45R1
-
CMOS equivalent of Motorola 6845R1 Enhanced
CRTC
— 68C45S
-
CMOS equivalent of Hitachi 6845S CRTC
-- 68C45SY
-
CMOS CRTC similar to Synertek 6545 CRTC
o 4.5 MHz video memory interface
o 3 MHz system processor interface
o Compatible with the VTI bus architecture
o Programmable Display Enable and Cursor delays
(standard for
S
and SY versions
—
optional for
R
and
Rl versions)
o Programmable Vertical Sync pulse width
(standard for
S
version
—
optional for R, Rl and SY
versions)
o Row/Column display memory addressing (SY version)
o Double Width character control
OPTIONAL FEATURES
o 16K, 32K, or 64K display Memory Address range (14, 15, or
16 bits)
o 7, 8, or
9-bit
Vertical Row counter
VTI MEGACELLS
Megacells are building block equivalents of standard LSI
functions that can be combined with other megacells,
standard cells or compiled cells to create custom
User-Specific ICs
(USICs).
Megacells are fully compatible
with VTI's other cell technologies and design tools.
The VTI bus (TM) architecture allows multiple megacells to
be combined on
a
single IC, along with additional cells from
VTI's extensive libraries
—
decreasing the design time,
design cost, and size of complex systems.
A
detailed
Functional Model provided with each megacell further reduces
design verification time.
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