Tandy 1000 HX - Page 52

• TANDY COMPUTER PRODUCTS •
47
0008
Bit
0
1
2
3
4
5
6
7
Bit
0
1
2
3
4
5
6
7
0009
Bit
0-1
2
3-7
DMA Controller
IOW* = 0, Write Command Register
Description
0 = Memory to Memory Disable
1 = Memory to Memory Enable
0 = Channel 0 Address Hold Disable
1 = Channel 0 Address Hold Enable
X If bit 0=0
0 = Controller enable
1 = Controller disable
0 = Normal timing
1 = Compressed timing
X If bit 0=1
0 = Fixed priority
1 = Rotating priority
0 = Late write selection
1 = Extended write selection
X = If bit 3=1
0 = DREQ sense active high
1 = DREQ sense active low
0 = DACK sense active low
1 = DACK sense active high
IOR* = 0, Read Status Register
Description
1 = Channel 0 has reached TC
1 = Channel 1 has reached TC
1 = Channel 2 has reached TC
1 = Channel 3 has reached TC
1 = Channel 0 Request
1 = Channel 1 Request
1 = Channel 2 Request
1 = Channel 3 Request
DMA Controller
IOW* = 0, Write Request Register
Description
Bitl BitO
0 0 Select channel 0
0 1 Select channel 1
1 0 Select channel 2
1 1 Select channel 3
0 Reset request bit
1 Set request bit
Don't Care
IOR* = 0, Illegal