TANDY COMPUTER PRODUCTS •
49
OOOD
OOOE
OOOF
Bit
0
1
2
3
4-7
OO1O
-
001F
Address
0020
Note:
Bit4
= 1:
DMA Controller
IOW*
=
0, Master Clear
IOR*
=
0, Read Temporary Register
DMA Controller
IOW*
=
0, Clear Mask Register
IOR*
=
0, Illegal
DMA Controller
IOW*
=
0, Write all Mask Register Bits
Description
0
=
Clear channel
0
mask bit (Enable)
1
=
Set channel
0
mask bit (Disable)
0
=
Clear channel
1
mask bit (Enable)
1
=
Set channel
1
mask bit (Disable)
0
=
Clear channel
2
mask bit (Enable)
1
=
Set channel
2
mask bit (Disable)
0
=
Clear channel
3
mask bit (Enable)
1
=
Set channel
3
mask bit (Disable)
Don't care
IOR*
=
Illegal
Not Used
Description
8259A Interrupt Controller
Initialization Words are setup
by
the operating
system and are generally not
to be
changed.
Writing
an
initialization word may cancel pending
interrupts.
INITIALIZATION COMMAND WORD
1
BitO
=
0: ICW4 needed
= 1: ICW4 not needed
Bitl
=
0: Cascade Mode
= 1: Single
Bit2
=
Not used
Bit3
=
0: Edge Triggered Mode
= 1: Level Triggered Mode
when the
SL
bit
is
active
Bit5
-
7: Not Used
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