Technics SL-P2000

e 1C301 (MN6626): Digital signal processor
0
Division
Reference current input
RF signal input
DSL bias terminal
(Not used, open)
IREF
A
>
<
i) n”
RF
DRF
> <
oO
iw]
DSLF DSL loop filter sterminal
PLLF PLL loop filter terminal
Power supply terminal
RF signal polarity setting
RSEL terminal
(Not used, connected to VDD)
TBUS7
5 Test terminal
TBUSO
N
Flag terminal (Not used, open)
Interpolation flag terminal
(Not used, open)
(Not used, open)
area
tie
a
Ea
| oO
ae
pees
Digital audio signal
8 [eetieset |
ce fecera
(Not used, open)
oe
| oo |
| oT
ie
| 0
a
IPFLAG
19 FCLK
nce
K
K
ND
wo <
+
2)
A
23
24
(Not used, open)
Crystal OSC terminal
(f= 16.9344 MHz)
(Not used, open)
D
z | ScK
Rox
LRCK
z
<7
Frequency division clock signal
(Not used, open)
1 =
(f= 7g5 x CK=88.2kH2)
Test terminal
(Connected to GND)
to
Crystal OSC terminal
(f= 16.9344 MHz)
Crystal OSC terminal
(f = 16.9344 MHz)
(Not used, open)
3
Sub-code Q data
Sub-code Q register clock
n
Cc oO
2)
3
34
35
36
~N
SL-P2000
Hte)
Division
Sub-code frame clock
(f=735kHz) (Not used, open)
Sub-code biock clock (f=75Hz)
ICLDCK
BLKCK
DEMPH
eo
Lay
ce
iene
as
IE tized
eso
[=f
SUBC
oe
De-emphasis ON signal
(“H”: ON)
Emphasis signal
Command load signal
(“L": LOAD)
Command clock signal
Command data signal
Muting input ('‘‘H": MUTE)
System clock (f=4.2336 MHz)
=
oO
ae x
Status signal
(CRC, CUE, CLVS, TTSTOP,
FCLV, SQOK)
Sub-code CRC check terminal
(“H": OK, “L” NG)
(Not used, open)
Sub-code serial output data
(Not used, open)
Sub-code serial output clock
sBon (Not used, open)
Tracking servo ON signal
(Ls ON)
Turntable servo phase synchro
signal
(“H": CLV, “L": Rough servo)
ITRON
CLVS
Turntable motor ON signal
(“L": ON)
Turntable motor drive signal
(Forced mode)
Turntable motor drive signal
(Servo error signal)
Power supply terminal
Test terminal (Norma: “H”)
R
B
DD
SSEL
38
39
40
41
42
43
44
45
47
52
53
54
55
7 5
“SUBQ” terminal mole select
(“H": Q code buffer)
“SMCK” terminal frequency
select ("L”: SMCK =42336 MHz)
= n m rm
Re-synchronizing sigal of :
frame sync. (Not use, open)
Be} m n
<
Drop-out detection sig mal
| co | Ce : prop:suy
EFM EFM signal (Not usej, open)
PLL extract clock
Pek (f = 4.3218 MHz)
(Not used, open)
Phase comparated sy mal of
EFM and PCK (Not wed, open)