Technics SL-PC25

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1C301
(MN6625):
Digital
signal
processor
Serial data byte clock
(Not used, open)
Crystal frame clock
(Not used, open)
De-emphasis ON signa!
(de-emphasis ON at “H”’)
G Lchannel deglitch signal
(Not used, open)
| moe R channel deglitch signal
IPFLAG
u
(Not used, open)
FLAG
Bane
ae [od
prox |e
SRDATA
SRCK
Interpolation flag
{interpolation at “H”’)
Error flag terminal
Clock (16.9344MHz) output
(Not used, open)
Test mode selection
(Not used, connected to +5V)
13
Digital signal output
(Not used, open)
Mode selector
(“L’:normal, “’H’’: SLEEP mode)
(Not used, connected to GND)
Test terminal (’L’’: normal)
(Not used, connected to GND)
Ciock input (16.9344 MHz)
Clock output (16.9344MHz)
(Not used, open)
GND terminal
Sub-code block (Q data)
clock (75 Hz)
clock (7.35 kHz)
Di
(eo)
x
“LT _
S:
L
K
T
D
BLKCK
CLOCK
af
Division
ooo
a
fess
Tracking servo ON signal
(tracking servo ON at “L”’)
Processing condition
(CRC, CUE, CLVS, TT STOP, FCLV)
Sub-code serial output data
(Not used, open)
Clock for sub-code serial output
(Not used, open)
oe Clock output (4.2336 MHz)
DATA
27 MUTE
STAT
SUBC
SBCK
SMCK
fsa | =] = =
3 2
z x
Vv
Power supply (connected to +5V)
Emphasis signal input
(Not used, open)
Spindle motor FG signal input
(Not used, open)
Spindle motor ON signal
(ON at “L”)
wo N
Spindle motor drive signal
Resynchronizing signal
(Not used, open)
RESY
Drop-out signal (Drop-out at “H”’)
EFM signal input (DSL)
EFM signal input (PLL)
PLL extract clock input
(4.3218 MHz)
Pi
>
wo
FE PLL frequency comparision signal
vO 16K RAM data input/output
=f
fee
= ee
=[e]
eal
on
yer
=f]
7c
§
DO
16K RAM OE signal
16K RAM WE signal
16K RAM address signal
(RAMAO: LSB, RAMA10: MSB)
RAM/OE
RAM/WE
RAM/AO
i)
RAM/A10
ae
eels