Technics SL-PD647

10
Division
hb
»
3
Double velocity status signal
(“H”: double)
RF signal input
Reference current input
DSL bias terminal
(Not used, open)
DSL loop filter terminal
PLL loop filter terminal
VCO loop filter terminal
(Not used, open)
Power supply (analog circuit)
terminal (2)
GND (analog circuit) terminal
EFM signal (Not used, open)
PLL extract clock
(f = 4.3218 MHz)
= <
mi m
ARF
45 IREF
DRF
b [o>]
od <
z
P 7"
47 DSLF 1/0
PLLF 10
48 I
49 vO
PCK
Phase comparated signal of
EFM and PCK
(Not used, open)
Sub-code serial output data
(Not used, open)
no
UBC
oa a
Sub-code serial output clock
SBCK (Not used, connected to GND)
a N
Vss
x<
ele
N _
Crystal oscillator terminal
(f= 16.9344 MHz)
Power supply terminal
Byte clock signal
(Not used, open)
Sub-code frame clock signal
(f CLDCK=7.35 kHz: Normal)
(Not used, open)
Vop
oO
61 YTCK
62 ICLDCK
SL-PD647
/0-
Division
Crystal frame clock
(Not used, open)
Interpolation flag terminal
Flag terminal :
Turntable servo phase synch.
signal _
(“H”: CLV, “L”: Rough servo)
(Not used, open)
FCLK
=|
pe
je FLAG
CLVS
IPFLAG
CRC
Sub-code CRC check terminal
(“H”: OK, st aged NG)
De-emphasis ON signal
(“H”: ON)
(Not used, open)
Re-synchronizing signal of
frame sync.
(Not used, open)
Reset terminal after “MASH”
circuit ;
Test terminal
(Normal: “H”) ;
Power supply (analog circuit)
terminal (1)
Lch audio signal .
GND (analog circuit)
terminal (1)
Rch audio signal
‘Polarity direction control
terminal of RF signal j
Frequency control terminal of
crystal oscillator
(Not used, connected to GND)
Test terminal
(Normal: “L”)
“SMCK”" terminal frequency
select
(“L”: SMCK=4.2336 MHz)
“SUBQ” terminal mode select
(“H”: Q code buffer)
DEMPH
RESY
rep)
Ni
70 IRST2
71 ITEST
72 Vpo1
73 UTL
4 V1
75 UTR
pa | |
RSEL |
QO
”
no m r
77 SEL
78 PSEL
79 MSEL