Technics SL-PS670A

@ IC701 (AN8805SBE1)
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[=| REFSW | 7 [Gapasior connection for GROSS
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| 8] BAN AGC signal input
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RC
iT [CeNV | |Capactorconneston or AF detection |
2
Capacitor connection for HPF amplifier
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13 CSBDO Capacitor connection for-RF envelope
detection
Ld
CSBRT ei Capacitor connection for RF envelope
detection
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if | mrper | | RFDET signal output
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} 19} ENV |O) STENV signal output
|} 20 | VREF | 0 | VREF signal output
a) eer | APC OFF signal control
| 22] VDET |O| VDET signal output
[2] TeePr fT | VDET signal input
| 24 | CROSS | 0 | CROSS signal output
| 25 | TEOUT | 0 | TE amplifier signal output
} 2] Te | TE amplifier inversion signal input
es
Ea
FE amplifier signal output
27 FEOUT (2 |
PFE FE amplifier inversion signal input
FBAL it | F BAL control signal
31 =|
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TE-
FE-
| 30 | TBA TBAL control signal
at | PDFR
PDER
ca
aT
sf eo
Pe [ac]
Adjustment for I-V amplifier conversion
resister
Adjustment for I-V amplifier conversion
resister
8
|-V amplifier signal input
ae
Gg -V amplifier signal input
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|-V amplifier signal input
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|-V amplifier signal input
SL-PS670A
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Name
} 1 | BCLK {0 | Bit clock output for serial data
LRCK laa LR identification signal output
SRDATA | Serial data output
DVdd1 =| Power supply input (for digital circuit)
| 5 | Dvssi | —|] GND (for digital circuit)
/s6 | XK [Oo] Digital audio interface signal output
+ MCLK Microprocessor command clock signal
input (Latches data at first transition)
8 MDATA ia Microprocessor command data signal
input
pe | mo ft] Microprocessor command load signal
input
Sense signal output
10 SENSE (OFT, FESL, MAGEND, NAJEND,
POSAD, SFG)
Focus servo feeding signal output
EES | ("L’: Feed)
12 TLOCK Leas servo feeding signal output
("L’: Feed)
Sub-code block clock signal output
13 BLKCK (fBLKCK= 75 Hz during normal
playback) (noused, open)
Sack a External clock signal input for sub-code
Q resister
Status signal output
17 STAT (CRC, CUE, CLVS, TTSTVP, FCLV,
SQCKk)
Sa ee
1/4-divided clock signal of crystal
oscillating at MSEL =“L”
| TVD | O] Traverse drive output
Spindle motor ON signal output
| 27 | TRD |O| Tracking drive output
| 28] FOD |O | Focus drive output
1/2-divided clock signal of crystal
19 SMCK
(SMCK = 4.2336 MHz) (no used,open)
24 ECM Spindle motor drive signal output
(forced mode output)
D/A (drive) output (TVD, ECS, TRD,
VREF FOD, FBAL, TBAL) reference voltage
input
SUBQ | 0 | Sub-code Q code output
DMUTE || Muting input (“H”: Mute)
oscillating at MSEL =“H”
((SMCK = 8.4672 MHz)
1/192-divided clock signal of crystal
PMCK oscillating (PMCK= 88.2 kHz)
(no used,open)
21 | a | O| Traverse forced feed output
25 ECS Spindle motor drive signal output
(servo error signal output)
KICK | 0 | Kick pulse output
Focus balance adjustment output
| 31 | TBAL | O | Tracking balance adjustment output
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SL-PS670A |
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Terminal
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Focus error signal input (analog input)
Tracking error signal input
(analog input)
RF envelope signal input
€
EDECRIERE
RFENV
Vibration detection signal input
= ("H": detection)
Off-track signal input ("H”: off track)
T
RF detection signal input
eet (“L’: detection)
| BDO | Dropout signal input (“H”: Dropout)
Laser onsignal output (“H”: ON)
Y
L
Tracking error shunt signal output
("H”: shunt) (no used, open)
Play signal out ("H”: PLAY)
(no used, open)
3
41
8
42
Double speed status signal output
("H": Double speed) (no used, open)
FE
E
FT
BDO
le)
TES
ea
aes
[ABET | sinat input
EF [1 [Reterence eurentinpat
| BAF || DSL bias (no used, open)
PLLF
EFM
CK
ss
x1
X2
dd
47 DSLF DSL loop filter
Ry /O }PLL loop filter
VCOF VCO loop filter
AVdd2 Power supply input (for analog circuit)
r
o
BE
[TRORS [7 [rsccass straint
Fa
g
=]
[Ave [= |S Worarabg ora |
=]
EFM signal output (not used, open)
PLL extraction clock output
Pi (fPCK= 4.321MHz during normal
playback) (no used, open)
Phase comparison signal of EFM and
PCK signals (no used, open)
| suc Sub-code serial data output
aane (no used, open)
Clock input for sub-code serial data
SBCK
Vi
rystal oscillating circuit input
(f= 16.9344MHz)
2 0
Crystal oscillating circuit output
(f= 16.9344MHz)
ail
ir
Bia supply input (for oscillating
ircuit)
i
Vi
BYTCK
/CLDCK
FCLK
IPFLAG
FLAG
ie]
= @
yte clock output (no used, open)
ub-code frameclock signal output
(f(CLDCK = 7.35kHz during normal
playback)
Crystal frame clock signal output
(fFCLK = 7.35kHz, double = 14.7kHz)
Interpolation flag output
("H": Interpolation) (no used, open)
Flag output (no used, open)
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Terminal
Name
Spindle servo phase synchronizing
CLVS
signal output
iC
("H”: CLV, “L”: rough servo)
DEMPH
(no used, open)
Sub-code CRC checked output
("H": OK, “L”: NG) (no used, open)
De-emphasis ON signal output
("H": ON) (no used, open)
Frame resynchronizing signal output
RESY (no used, open)
IRST2 Reset input through MASH circuit
cR
pose | [iow
TEST
OUT
67
3{e{elal @ |Fe
EB
=
| ¥ | Test input
AVdd1 | Power supply input (for analog circuit)
| OUTL, | 0 | Left channel audio signal output
Avssi | — |
ala
0
4
OUTR
Right channel audio signal output
FF signal polarity assignment input
RSEL
7 CSEL
(at'“H” level: RSEL = “H”)
PSEL
(at “L” level: RSEL =“L”)
MSEL
7
7
75
6 7
Crystal oscillating frequency
designation input
("L’: 16.93844MHz, “H”: 33.8688MHz)
Test input (normally, “L”)
Output frequency switching for SMCK
terminal
“H”, SMCK = 8.4672MHz
“L’. SMCK = 4.2336MHz
Output mode switching of SUBQ
terminal ("H”: Q code buffer mode)
SSEL
90