AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
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Table 6-75. Additional SPI0 Slave Timings, 5-Pin Option
(1)(2)(3)
(continued)
1.3V, 1.2V 1.1V 1.0V
NO. PARAMETER UNIT
MIN MAX MIN MAX MIN MAX
Polarity = 0, Phase = 0,
2.5P+17.5 2.5P+20 2.5P+27
from SPI0_CLK falling
Polarity = 0, Phase = 1,
Delay from final clock receive
2.5P+17.5 2.5P+20 2.5P+27
from SPI0_CLK rising
edge on SPI0_CLK to slave 3-
30 t
dis(SPC_ENA)S
ns
stating or driving high
Polarity = 1, Phase = 0,
2.5P+17.5 2.5P+20 2.5P+27
SPI0_ENA.
(4)
from SPI0_CLK rising
Polarity = 1, Phase = 1,
2.5P+17.5 2.5P+20 2.5P+27
from SPI0_CLK falling
(4) SPI0_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is tri-stated. If tri-stated, an external pullup resistor should
be used to provide a valid level to the master. This option is useful when tying several SPI slave devices to a single master.
160 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated
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