Texas Instruments AM1808 - Page 221

I1
21 3
5
4
7
6
9
Q1 I2 I3 I4 I5 I6 I7 I8 I9Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
8
CHx_CLK
CHx_START
CHx_ENABLE
CHx_DATA[n:0]
CHx_XDATA[n:0]
CHx_WAIT
11
10
CHx_CLK
CHx_START
CHx_ENABLE
CHx_DATA[n:0]
CHx_XDATA[n:0]
Data2Data1 Data3 Data4
2
CHx_WAIT
Data5 Data6
1
Data7 Data8 Data9
3
5
4
7
6
9
8
AM1808
www.ti.com SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
Figure 6-69. uPP Single Data Rate (SDR) Receive Timing
Figure 6-70. uPP Double Data Rate (DDR) Receive Timing
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