Texas Instruments AM1808 - Page 222

I1
15
13
17
16
12 14
2019
Q1 I2 I3
I4
I5 I6 I7 I8 I9Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
18
CHx_CLK
CHx_START
CHx_ENABLE
CHx_DATA[n:0]
CHx_XDATA[n:0]
CHx_WAIT
Data2Data1 Data3 Data4
15
13
17
16
Data5 Data6
12
Data7 Data8 Data9
14
2019
CHx_CLK
CHx_START
CHx_ENABLE
CHx_DATA[n:0]
CHx_XDATA[n:0]
CHx_WAIT
AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014 www.ti.com
Figure 6-71. uPP Single Data Rate (SDR) Transmit Timing
Figure 6-72. uPP Double Data Rate (DDR) Transmit Timing
222 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated
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