AM1808
SPRS653E –FEBRUARY 2010–REVISED MARCH 2014
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6.7.1.4 AINTC System Interrupt Assignments
Table 6-6. AINTC System Interrupt Assignments
System Interrupt Interrupt Name Source
0 COMMTX ARM
1 COMMRX ARM
2 NINT ARM
3 PRU_EVTOUT0 PRUSS Interrupt
4 PRU_EVTOUT1 PRUSS Interrupt
5 PRU_EVTOUT2 PRUSS Interrupt
6 PRU_EVTOUT3 PRUSS Interrupt
7 PRU_EVTOUT4 PRUSS Interrupt
8 PRU_EVTOUT5 PRUSS Interrupt
9 PRU_EVTOUT6 PRUSS Interrupt
10 PRU_EVTOUT7 PRUSS Interrupt
11 EDMA3_0_CC0_INT0 EDMA3_0 Channel Controller 0 Shadow Region 0 Transfer
Completion Interrupt
12 EDMA3_0_CC0_ERRINT EDMA3_0 Channel Controller 0 Error Interrupt
13 EDMA3_0_TC0_ERRINT EDMA3_0 Transfer Controller 0 Error Interrupt
14 EMIFA_INT EMIFA
15 IIC0_INT I2C0
16 MMCSD0_INT0 MMCSD0 MMC/SD Interrupt
17 MMCSD0_INT1 MMCSD0 SDIO Interrupt
18 PSC0_ALLINT PSC0
19 RTC_IRQS[1:0] RTC
20 SPI0_INT SPI0
21 T64P0_TINT12 Timer64P0 Interrupt 12
22 T64P0_TINT34 Timer64P0 Interrupt 34
23 T64P1_TINT12 Timer64P1 Interrupt 12
24 T64P1_TINT34 Timer64P1 Interrupt 34
25 UART0_INT UART0
26 - Reserved
27 MPU_BOOTCFG_ERR Shared MPU and SYSCFG Address/Protection Error Interrupt
28-31 - Reserved
32 EDMA3_0_TC1_ERRINT EDMA3_0 Transfer Controller 1 Error Interrupt
33 EMAC_C0RXTHRESH EMAC - Core 0 Receive Threshold Interrupt
34 EMAC_C0RX EMAC - Core 0 Receive Interrupt
35 EMAC_C0TX EMAC - Core 0 Transmit Interrupt
36 EMAC_C0MISC EMAC - Core 0 Miscellaneous Interrupt
37 EMAC_C1RXTHRESH EMAC - Core 1 Receive Threshold Interrupt
38 EMAC_C1RX EMAC - Core 1 Receive Interrupt
39 EMAC_C1TX EMAC - Core 1 Transmit Interrupt
40 EMAC_C1MISC EMAC - Core 1 Miscellaneous Interrupt
41 DDR2_MEMERR DDR2 Controller
42 GPIO_B0INT GPIO Bank 0 Interrupt
43 GPIO_B1INT GPIO Bank 1 Interrupt
44 GPIO_B2INT GPIO Bank 2 Interrupt
45 GPIO_B3INT GPIO Bank 3 Interrupt
46 GPIO_B4INT GPIO Bank 4 Interrupt
47 GPIO_B5INT GPIO Bank 5 Interrupt
82 Peripheral Information and Electrical Specifications Copyright © 2010–2014, Texas Instruments Incorporated
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