Digital PFC Description
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12.7 System Protection
12.7.1 Cycle-by-Cycle Current Protection (CBC)
The cycle-by-cycle current protection is achieved through AD04 (Comparator D) and AD13 (Comparator
E). Once the current signal has exceeded the threshold, the PWM is chopped to limit the current.
12.7.2 Over-Voltage Protection (OVP)
There are two levels of OVP that exist. Under fault condition if the output voltage reaches 420 V, a non-
latched OV protection is activated. Under this condition the output oscillates between 420 V and 380 V.
In the event of a more severe overvoltage condition, if the output reaches to 435 V, the latched over-
voltage protection is activated and the unit is completely shut off.
The FIQ is currently used only for latched over-voltage protection. It is triggered by the comparator on
AD06 (Comparator F). Comparator F’s threshold is set above the limit for the DC bus voltage, and the
logic on DPWM1 and DPWM2 is set up to turn off DPWM1B and DPWM2B when the threshold is
exceeded. In the current configuration, the only way to restart the PFC after a latched OVP fault is to reset
the processor.
12.8 PFC System Control
The system control block diagram is shown in Figure 38. In steady state, the average current-mode
control is used with switching frequency fixed at 100 kHz. At low line below 160 V
AC
and light load, ZVS
and valley control is used to reduce the switching losses and reduce total harmonic distortion.
Figure 38. Single-Phase PFC System Control Diagram
40
Digitally Controlled Single-Phase PFC Pre-Regulator SLUU885B–March 2012–Revised July 2012
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Copyright © 2012, Texas Instruments Incorporated
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