u-blox LEA-5 Series - Page 21

LEA-5, NEO-5, TIM-5H - Hardware Integration Manual
GPS.G5-MS5-09027-A2 Released Hardware description
Page 21 of 68
1.5.4.5 Pin configuration with u-blox 5 module as one of several slaves
SPI Slave
X
MOSI
X
u-blox 5
GPS Receiver
(SPI Slave
1
)
VDD_IO
SS_N
MOSI
(CFG_COM0)
MISO
(CFG_COM1)
SCK
(CFG_GPS0)
GND
Microprocessor
(SPI Master)
SPI
Chip
Select
DATA_OUT_SPI
SPI_Clock
DATA_IN_SPI
A
A
A
Y
Y
Y
OE
OE
OE
CS
X
N
CS
2
N
CS
1
N
Chip_Select
X
SPI Slave
2
Chip_Select
2
SCK
X
SCK
2
MOSI
2
MISO
X
MISO
2
U
1
U
2
U
3
Figure 12: Diagram of SPI Pin Configuration
Component
Description
Model
Supplier
U
1
– U
3
Buffer
NC7SZ125
Fairchild
Figure 13: Recommended components for SPI pin configuration
Use same power voltage to supply U
1
– U
3
and VDD_IO.