ZiLOG Z80 Handbook

16-BIT MEMORY ADDRESS
OR DOUBLE
- PRECISION VALUE
REGISTER PAIR
B(B 1
C(C 1
B, C
REGISTER PAIR
D, E
DID 1
E(E 1
REGISTER PAIR
L
H
H(H 1
LIL )
,
8 H IGH-ORDER BITS 8 LOW-ORDER B ITS
Fig. 2-4
. Register pairs.
Double-precision arithmetic involves adding, subtracting, incre-
menting (adding one), or decrementing (subtracting one) a 16-bit
value. Most arithmetic and logical operations in the Z-80 are oriented
towards 8-bit operations, but the Z-80 allows limited operations be-
tween the register pairs and the stack pointer and index registers IX
and IY. The general philosophy for this probably evolved from the
requirement to manipulate memory address pointers in some con-
venient fashion, since all external memory addresses are 16-bit ad-
dresses and two 8-bit operations would have to be performed if 16-
bit arithmetic were not implemented. Fig. 2-5 shows the use of the
register pairs in double-precision operations.
16-B IT RESULT
ALU
ADD, SUBTRACT,
INCREMENT
,
DECREMENT
I -
f _f
OPERAND ANDI OPERAND 2
_l-t
I
B,C REGISTER PAIR
D, E REGISTER PAIR
H, L REGISTER PAIR
SP
IX
IY
FLAG S
Fig. 2-5. Register pair double-
precision operation.
FLAG REGISTER
The flag register is selected along with the A register. At any given
time A and F or A' and F' are selected. Although the
flag
register is
a register of eight bits as are the other seven CPU registers, it is more
a collection of eight bits conveniently grouped into one register than
a general-purpose register. The bits within the flag register specify
various CPU conditions that have occurred after an arithmetic, logi-
cal, or other CPU operation. For example, it is convenient to know
if the result of the addition of two operands resulted in a zero result,
18

ZiLOG Z80 Specifications

General

Manufacturer	ZiLOG
Introduction Year	1976
Clock Speed	2.5 MHz to 20 MHz
Data Width	8-bit
Address Width	16-bit
Instruction Set	Z80
Transistor Count	8, 500
Package	40-pin DIP
Category	Microprocessor
Memory Address Space	64 KB
Voltage Supply	5V