ZiLOG Z80 Handbook

of stack operation is a LIFO operation, or last in, first out. The con-
tents of the SP during a typical instruction sequence is shown in
Fig. 2-8. Note that the stack builds from higher numbered memory
to lower numbered memory as more data is stored in the stack.
The remaining registers of the Z-80 are not contained in the 8080.
The index registers IX and IY are two 16-bit registers that permit
indexed addressing in Z-80 programs. While the 8080 had indexed-
like instructions, it did not permit true indexing. When an instruction
is executed in an indexed addressing mode, one of the two index
registers is used to calculate the memory address of the operand.
Fig. 2
-
8. Stack Pointer ( SP) operation.
MEMORY STACK
(STACK) POINTER
LOCATION CONTENTS
0103
0102 I I 0103
0100
0101
(1) PUSH DATA A
0100
0101
0102 OA
TAA
0103 (2) PUSH DATA B
0100
0101
0102
0103
0100
0101
0102
0103
DATA B
DATA A
(3) PULL DATA B
DATA C2
DATA C1
DATA A
14) PUSH DATA C
(TWO BYTES)
0102
0103
0101
The
effective address
of the memory operand is obtained by adding
the contents of the index register and a 16-bit value contained in the
displacement field
of the instruction employing the indexed address-
ing mode. Indexed operations of this kind are extremely powerful
for efficient programming and will be discussed in more detail later.
The Interrupt Vector Register I is an
8-bit register that can be
loaded with 8 bits of data specifying a memory address. This ad-
dress, when combined with a lower-order 8 bits of address supplied
by the interrupting device, represent a memory address whose con-
tents
in turn
specify the memory address of the software
interrupt
handling
routine
for the device. Suppose that a paper-tape reader
21

ZiLOG Z80 Specifications

General

Manufacturer	ZiLOG
Introduction Year	1976
Clock Speed	2.5 MHz to 20 MHz
Data Width	8-bit
Address Width	16-bit
Instruction Set	Z80
Transistor Count	8, 500
Package	40-pin DIP
Category	Microprocessor
Memory Address Space	64 KB
Voltage Supply	5V