ZiLOG Z80 User Manual

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Address Bus (output, active High, tristate). A15-A0 form a 16-bit address
bus. The Address Bus provides the address for memory data bus
exchanges (up to 64 Kbytes) and for I/O device exchanges.
System
Control
CPU
Control
CPU
Bus
Control
Z80 CPU
Address
Bus
Data
Bus
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D3
D4
D5
D6
D7
D2
30
31
32
33
34
35
36
37
38
39
40
14
15
12
8
7
9
10
13
1
2
3
4
5
M1
MREQ
IORQ
RD
WR
RFSH
HALT
INT
NMI
RESET
BUSRQ
BUSACK
CLK
+5V
GND
WAIT
27
19
20
21
22
26
18
24
16
17
28
25
23
6
11
29

ZiLOG Z80 Specifications

General

Manufacturer	ZiLOG
Introduction Year	1976
Clock Speed	2.5 MHz to 20 MHz
Data Width	8-bit
Address Width	16-bit
Instruction Set	Z80
Transistor Count	8, 500
Package	40-pin DIP
Category	Microprocessor
Memory Address Space	64 KB
Voltage Supply	5V