ZiLOG Z80 User Manual

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Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the
requesting device that the CPU address bus, data bus, and control signals
MREQ
, IORQ RD, and WR have entered their high-impedance states.
The external circuitry can now control these lines.
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Bus Request (input, active Low). Bus Request has a higher priority than
NMI
and is always recognized at the end of the current machine cycle.
BUSREQ
forces the CPU address bus, data bus, and control signals
MREQ
IORQ, RD, and WR to go to a high-impedance state so that other
devices can control these lines. BUSREQ
is normally wired-OR and
requires an external pull-up for these applications. Extended BUSREQ
periods due to extensive DMA operations can prevent the CPU from
properly refreshing dynamic RAMS.
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Data Bus (input/output, active High, tristate). D7–D0 constitute an
8-bit bidirectional data bus, used for data exchanges with memory and I/O.
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HALT State (output, active Low). HALT indicates that the CPU has
executed a HALT instruction and is waiting for either a non-maskable or a
maskable interrupt (with the mask enabled) before operation can resume.
During HALT, the CPU executes NOPs to maintain memory refresh.
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Interrupt Request (input, active Low). Interrupt Request is generated by
I/O devices. The CPU honors a request at the end of the current
instruction if the internal software-controlled interrupt enable flip-flop
(IFF) is enabled. INT
is normally wired-OR and requires an external
pull-up for these applications.

ZiLOG Z80 Specifications

General

Manufacturer	ZiLOG
Introduction Year	1976
Clock Speed	2.5 MHz to 20 MHz
Data Width	8-bit
Address Width	16-bit
Instruction Set	Z80
Transistor Count	8, 500
Package	40-pin DIP
Category	Microprocessor
Memory Address Space	64 KB
Voltage Supply	5V