ZiLOG Z80 User Manual

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Input/Output Request (output, active Low, tristate). IORQ indicates that
the lower half of the address bus holds a valid I/O address for an I/O read
or write operation. IORQ
is also generated concurrently with M1 during
an interrupt acknowledge cycle to indicate that an interrupt response
vector can be placed on the data bus.
0
Machine Cycle One (output, active Low). M1, together with MREQ,
indicates that the current machine cycle is the opcode fetch cycle of an
instruction execution. M1
together with IORQ, indicates an interrupt
acknowledge cycle.
05(4
Memory Request (output, active Low, tristate). MREQ indicates that the
address bus holds a valid address for a memory read of memory write
operation.
10,
Non-Maskable Interrupt (input, negative edge-triggered). NMI has a
higher priority than INT
. NMI is always recognized at the end of the
current instruction, independent of the status of the interrupt enable flip-
flop, and automatically forces the CPU to restart at location
0066H.
5'
Read (output, active Low, tristate). RD indicates that the CPU wants to
read data from memory or an I/O device. The addressed I/O device or
memory should use this signal to gate data onto the CPU data bus.
5(6(7
Reset (input, active Low). RESET initializes the CPU as follows: it resets
the interrupt enable flip-flop, clears the PC and registers I and R, and sets

ZiLOG Z80 Specifications

General

Manufacturer	ZiLOG
Introduction Year	1976
Clock Speed	2.5 MHz to 20 MHz
Data Width	8-bit
Address Width	16-bit
Instruction Set	Z80
Transistor Count	8, 500
Package	40-pin DIP
Category	Microprocessor
Memory Address Space	64 KB
Voltage Supply	5V