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the interrupt status to Mode 0. During reset time, the address and data bus
go to a high-impedance state, and all control output signals go to the
inactive state. Notice that RESET
must be active for a minimum of three
full clock cycles before the reset operation is complete.
5)6+
Refresh (output, active Low). RFSH, together with MREQ indicates that
the lower seven bits of the system’s address bus can be used as a refresh
address to the system’s dynamic memories.
:$,7
WAIT (input, active Low). WAIT communicates to the CPU that the
addressed memory or I/O devices are not ready for a data transfer. The
CPU continues to enter a WAIT
state as long as this signal is active.
Extended WAIT
periods can prevent the CPU from properly refreshing
dynamic memory.
:5
Write (output, active Low, tristate). WR indicates that the CPU data bus
holds valid data to be stored at the addressed memory or I/O location.
&/.
Clock (input). Single-phase MOS-level clock.
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