Note 4 : test condition :
(1) V
DD
= 5 V, V
DD
rising time = 470 s ± 10%
(2) Pattern: Mosaic pattern
(3) Test circuit
Note 5 : LVDS signal definition
VIN
+
= Positive differential DATA & CLK Input
VIN- = Negative differential DATA & CLK Input
VID = VIN
+
– VIN- ,
∆VCM =VCM
+
–VCM-,
∆VID =VID
+
–VID-,
VID+ =VIH
+
–VIH-,
VID- =VIL
+
–VIL-,
VCM = (VIN
+
+VIN-)/2,
VCM+ = (VIH
+
+VIH-)/2,
VCM- = (VIL
+
+VIL-)/2,
90