Master Series Service Manual
The current memory map is dictated by the contents of the two latches,
ROM SELect and ACCess CONtrol located at &FE30 and &FE34 respectively.
The contents of these two latches are as follows:-
d7 d6 d5 d4 d3 d2 dl d0
(&FE30) RAM 0 0 0
PM3 PM2 PM1 PM0
(&FE34) IRR
TST IFJ ITU
Y X E D
The contents of ROMSEL dictate the selection of memory which resides
from &8000 to &BFFF.
ACCCON
The contents of ACCCON principally dictate the activity of two regions
of memory:
(a) &3000 to &7FFF
(b) &C000 to &DFFF
128 Kbyte RAM
The RAM is functionally split up into two regions: The main region
supports the language workspaces, buffers etc. and provides the bit
mapped screen. The second region provides four, 16K "Sideways" RAM
segments. These are
link selected into ROM locations 4,5,6 and 7. They
may be deselected,
reinstating the ROM sockets in "chunks" of 32
Kbyte.
Within the main 64 Kbyte region, the lower 32K is used within the
&0000 to &7FFF region of the CPU memory map, as shown in figure 1.
The upper 32K is split up into three, self-contiguous regions. The
largest portion of this is a 20 Kbyte region designated LYNNE. This
can be overlayed on the region (a) of main memory.
*
When bit D in ACCCON is set, the CRT controller will display the
contents of LYNNE. When bit D is cleared, the region (a) of main
memory will be displayed.
*
When bit E in ACCCON is set, if the address range is &3000 to &7FFF
the CPU will read/write Lynne according to the flow shown in figure 2.
15
Issue 1
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