Master Series Service Manual
In this way, fewer connections to the controller logic are required to
select agiven ROM, although the power dissipation will be increased if
all the ROMs in one column are inserted.
A chip select will be driven low if an access to one of the segments (
4 to 8) is required. If a cartridge ROM is required, then the
Cartridge ROM chip select will be driven high. All chip selects are a
decode of the CPU address most significant nibble.
An output enable is turned active low during the CPU phi2 period
depending on which segment is required.
The segment to be selected is determined by the binary number held
within the least significant nibble of ROMSEL.
Overlaid RAM in ROM area
When the bit RAM is set in ROMSEL, accesses to the region &8000 to
&8FFF are redirected from the currently selected ROM to a region of
RAM referred to as ANDY. It is the responsibility of the code which
set RAM to clear it after accessing ANDY. This is necessary to ensure
correct operation of software in ROM.
Summary of RAM memory map
The 64K of DRAM is distributed as follows:-
Figure 4
A further 64 Kbyte of RAM is available as four pages of 16 Kbyte from
&8000 to &BFFF. The ROM slots 4,5,6 and 7 are not active when this RAM
is link
selected to be active.
18
Issue 1
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