14 Pinouts and Signal Descriptions
3.3.3. LVDS/eDP
LVDS
Signal Pin Description I/O PU/PD Comment
LVDS_A0+
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS_A2+
LVDS_A2-
LVDS_A3+
LVDS_A3-
A71
A72
A73
A74
A75
A76
A78
A79
LVDS Channel A differential pairs O LVDS
LVDS_A_CK+
LVDS_A_CK-
A81
A82
LVDS Channel A differential clock O LVDS
LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
B71
B72
B73
B74
B75
B76
B77
B78
LVDS Channel B differential pairs O LVDS
LVDS_B_CK+
LVDS_B_CK-
B81
B82
LVDS Channel B differential clock O LVDS
LVDS is default.
(through eDP to LVDS
bridge)
Note: eDP support
available by build
option
LVDS_VDD_EN A77 LVDS panel power enable O 3.3V PD 10k
LVDS_BKLT_EN B79 LVDS panel backlight enable O 3.3V
LVDS_BKLT_CTRL B83 LVDS panel backlight brightness control O 3.3V PD 100k
ePD to LVDS
requirement
LVDS_I2C_CK A83
DDC lines used for flat panel detection and
control.
O 3.3V PU 2k2 3.3V
LVDS_I2C_DAT A84
DDC lines used for flat panel detection and
control.
I/O 3.3V PU 2k2 3.3V
eDP (build option)
Signal Pin Description I/O PU/PD Comment
eDP_TX2+
eDP_TX2-
eDP_TX1+
eDP_TX1-
eDP_TX0+
eDP_TX0--
A71
A72
A73
A74
A75
A76
eDP differential pairs O PCIE AC coupled off module
eDP_TX3+
eDP_TX3--
A81
A82
eDP differential pairs O PCIE AC coupled off module
eDP_VDD_EN A77 eDP power enable O 3.3V PD 10k
eDP_BKLT_EN B79 eDP backlight enable O 3.3V
eDP_BKLT_CTRL B83 eDP backlight brightness control O 3.3V PD 100k
eDP_AUX+ A83 eDP AUX+ I/O PCIE AC coupled off module
eDP_AUX- A84 eDP AUX- I/O PCIE AC coupled off module
eDP_HPD A87
Detection of Hot Plug / Unplug and
notification of the link layer
I 3.3V PD 100k
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