ADLINK Technology cExpress-AL - Page 22

16 Pinouts and Signal Descriptions
3.3.6. PCI Express
Signal Pin Description I/O PU/PD Comment
PCIE_TX0+
PCIE_TX0-
A68
A69
PCI Express channel 0, Transmit
Output differential pair.
O
PCIE
AC coupled on module
PCIE_RX0+
PCIE_RX0-
B68
B69
PCI Express channel 0, Receive Input
differential pair.
I PCIE AC coupled off module
PCIE_TX1+
PCIE_TX1-
A64
A65
PCI Express channel 1, Transmit
Output differential pair.
O
PCIE
AC coupled on module
PCIE_RX1+
PCIE_RX1-
B64
B65
PCI Express channel 1, Receive Input
differential pair.
I PCIE AC coupled off module
PCIE_TX2+
PCIE_TX2-
A61
A62
PCI Express channel 2, Transmit
Output differential pair.
O
PCIE
AC coupled on module
PCIE_RX2+
PCIE_RX2-
B61
B62
PCI Express channel 2, Receive Input
differential pair.
I PCIE AC coupled off module
PCIE_TX3+
PCIE_TX3-
A58
A59
PCI Express channel 3, Transmit
Output differential pair.
O
PCIE
AC coupled on module
PCIE_RX3+
PCIE_RX3-
B58
B59
PCI Express channel 3, Receive Input
differential pair.
I PCIE AC coupled off module
PCIE_TX4+
PCIE_TX4-
A55
A56
PCI Express channel 4, Transmit
Output differential pair.
O
PCIE
AC coupled on module. PCIe port 4 is
by build option, by PCIe bridge IC
PCIE_RX4+
PCIE_RX4-
B55
B56
PCI Express channel 4, Receive Input
differential pair.
I PCIE
AC coupled off module. PCIe port 4 is
by build option, by PCIe bridge IC
PCIE_TX5+
PCIE_TX5-
A52
A53
PCI Express channel 5, Transmit
Output differential pair.
O
PCIE
AC coupled on module. PCIe port 5 is
by build option, in place of GbE
PCIE_RX5+
PCIE_RX5-
B52
B53
PCI Express channel 5, Receive Input
differential pair.
I PCIE
AC coupled off module. PCIe port 5 is
by build option, in place of GbE
PCIE_CLK_REF+
PCIE_CLK_REF-
A88
A89
PCI Express Reference Clock output
for all PCI Express and PCI Express
Graphics Lanes.
O
PCIE
Note: PCIe bridge IC is by build option to support more than 4 PCIe x1.
3.3.7. LPC Bus
Signal Pin Description I/O PU/PD Comment
LPC_AD[0:3] B4-B7
LPC multiplexed address, command and
data bus
I/O 3.3V
LPC_FRAME# B3
LPC frame indicates the start of an LPC
cycle
O 3.3V
LPC_DRQ0#
LPC_DRQ1#
B8
B9
LPC serial DMA request I 3.3V NC.
Not supported by Apollo
Lake
LPC_SERIRQ A50 LPC serial interrupt I/O 3.3V
PU 8k2
3.3V
LPC_CLK B10 LPC clock output –33MHz nominal O 3.3V
The LPC_CLK frequency
is 25MHz