29
Clock rate 100 Hz to 60 MHz
Supported data patterns PN9, 11, 15, 20, 23
Resolution 10 digits
Bit sequence length 100 bits to 4.294 Gbits after synchronization
Features
Input clock phase adjustment and gate delay
Adjustable input threshold
Hi/lo threshold selectable from 0.7 V [TTL], 1.4 V [TTL]
1.65 V [CMOS 3.3], 2.5 V [CMOS 5.0]
Direct measurement triggering
Data and reference signal outputs
Real-time display
Bit count
Error-bit-count
Bit error rate
Pass/fail indication
Valid data and clock detection
Automatic re-synchronization
Special pattern ignore
Specifications for Signal Personality Characteristics
Bit error rate [BER] analyzer
[Option UN7]
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