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The Standard Event Status Register is read and cleared by the *ESR? query, which returns a
decimal number corresponding to the contents. On power-up or initialisation after standby it is set to
128, to report the power-on bit.
The Standard Event Status Enable Register provides a mask between the Event Status Register
and the Status Byte Register. If any bit becomes ‘1’ in both registers, then the ESB bit will be set in
the Status Byte Register. This enable register is set by the *ESE
<NRF> command to a value 0 - 255,
and read back by the *ESE? query (which will always return the value last set by the controller). On
power-up it is set to 0.
15.3 Execution Error Register (EER)
This instrument specific register contains a number representing the last command processing error
encountered over this interface. The error numbers have the following meaning:
0 No error has occurred since this register was last read.
101 Numeric Error: the parameter value sent was outside the permitted range for the
command in the present circumstances.
102 Mode Error: the secondary display measurement requested is not compatible with the
primary measurement.
103 Function Error: the function (modifier) requested is not compatible with the primary
measurement.
The Execution Error Register is read and cleared using the ‘EER?’ command. On power up this
register is set to 0 for all interface instances.
There is no corresponding mask register: if any of these errors occurs, then bit 4 of the Standard
Event Status Register will be set. This bit can be masked from any further consequences by
clearing bit 4 of the Standard Event Status Enable Register.
15.4 Status Byte Register (STB) and GPIB Service Request Enable
Register (SRE)
These two registers are implemented as required by the IEEE Std. 488.2.
Any bits set in the Status Byte Register which correspond to bits set in the Service Request Enable
Register will cause the RQS/MSS bit to be set in the Status Byte Register, thus generating a
Service Request on the bus.
The Status Byte Register is read either by the *STB? query, which will return MSS in bit 6, or by a
Serial Poll which will return RQS in bit 6. The Service Request Enable register is set by the *SRE
<NRF> command and read by the *SRE? query.
Bits 7, 3, 2 and 0: Not used, permanently 0.
Bit 6 MSS/RQS. This bit (as defined by IEEE Std. 488.2) contains alternatively the
Master Status Summary message returned in response to the *STB? query, or the
Requesting Service message returned in response to a Serial Poll.
The RQS message is cleared when polled, but the MSS bit remains set for as long
as the condition is true.
Bit 5 ESB. The Event Status Bit. This bit is set if any bits set in the Standard Event Status
Re
ister correspond to bits set in the Standard Event Status Enable Re
ister.
Bit 4 MAV. The Message Available Bit. This will be set when the instrument has a
response message formatted and ready to send to the controller.
The bit will be cleared after the Response Messa
e Terminator has been sent.
Bit 1 INTR. The Input Trip Bit. This bit is set if any bits set in the Input Trip Register
correspond to bits set in the Input Trip Enable Register.
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