Altera DE1-SoC - Using the DE1-SoC Board; Configuring FPGA Mode Settings

DE1-SOC COMPUTER SYSTEM WITH NIOS II For Quartus II 15.0
/********************************************************************************
* Subroutine to read a character from the JTAG UART
* Returns \0 if no character, otherwise returns the character
********************************************************************************/
char get_jtag( void )
{
volatile int * JTAG_UART_ptr = (int *) 0xFF201000; // JTAG UART address
int data;
data = *(JTAG_UART_ptr); // read the JTAG_UART data register
if (data & 0x00008000) // check RVALID to see if there is new data
return ((char) data & 0xFF);
else
return (’\0’);
}
Figure 13. An example of C code that uses the JTAG UART (Part b).
2.6 Interval Timers
The DE1-SoC Computer includes a timer module implemented in the FPGA that can be used by the Nios II pro-
cessor. This timer can be loaded with a preset value, and then counts down to zero using a 100-MHz clock. The
programming interface for the timer includes six 16-bit registers, as illustrated in Figure 14. The 16-bit register at
address 0xFF202000 provides status information about the timer, and the register at address 0xFF202004 allows
control settings to be made. The bit fields in these registers are described below:
• TO provides a timeout signal which is set to 1 by the timer when it has reached a count value of zero. The TO
bit can be reset by writing a 0 into it.
• RUN is set to 1 by the timer whenever it is currently counting.
• ITO is used for generating interrupts, which are discussed in section 3.
• CONT affects the continuous operation of the timer. When the timer reaches a count value of zero it auto-
matically reloads the specified starting count value. If CONT is set to 1, then the timer will continue counting
down automatically. But if CONT = 0, then the timer will stop after it has reached a count value of 0.
• (START/STOP) is used to commence/suspend the operation of the timer by writing a 1 into the respective bit.
The two 16-bit registers at addresses 0xFF202008 and 0xFF20200C allow the period of the timer to be changed
by setting the starting count value. The default setting provided in the DE1-SoC Computer gives a timer period
of 125 msec. To achieve this period, the starting value of the count is 100 MHz × 125 msec = 12.5 × 10
6
. It is
possible to capture a snapshot of the counter value at any time by performing a write to address 0xFF202010. This
write operation causes the current 32-bit counter value to be stored into the two 16-bit timer registers at addresses
0xFF202010 and 0xFF202014. These registers can then be read to obtain the count value.
A second interval timer, which has an identical interface to the one described above, is also available in the FPGA,
starting at the base address 0xFF202020. Each Nios II processor has exclusive access to two interval timers.
Altera Corporation - University Program
2015
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